• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.31-40
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• 2016

In this paper, we analyse the characteristics of the edge image and propose a new entropy coding optimized to the compression of the edge image. The pixel values of the edge image have the Gaussian distribution around '0', and most of the pixel values are '0'. By using this analysis, the Zero Block technique is utilized in spatial domain. And the Intra Prediction Mode of the edge image is similar to the mode of the surrounding blocks or likely to be the Planar Mode or the Horizontal Mode. In this paper, we make use of the MPM technique that produces the Intra Prediction Mode with high probability modes. By utilizing the above properties, we design a new entropy coding method that is suitable for edge image and perform the compression. In case the existing compression techniques are applied to edge image, compression ratio is low and the algorithm is complicated as more than necessity and the running time is very long, because those techniques are based on the natural images. However, the compression ratio and the running time of the proposed technique is high and very short, respectively, because the proposed algorithm is optimized to the compression of the edge image. Experimental results indicate that the proposed algorithm provides better visual and PSNR performance up to 11 times than the JPEG.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.117-120
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• 2001

Synthetic aperture radar (SAR) is a promising active remote sensing technique to obtain large terrain information of the earth in all-weather conditions. SAR is useful in many applications, including terrain mapping and geographic information system (GIS), which use SAR display images. Usually, these applications need the enormous data storage because they deal with wide terrain images with high resolution. So, compression technique is a useful approach to deal with SAR display images with limited storage. Because there is some indispensable data loss through the conversion of a complex SAR image to a display image, some applications, which need high-resolution images, cannot tolerate more data loss during compression. Therefore, lossless compression is appropriate to these applications. In this paper, we propose a novel lossless compression technique for a SAR display image using one-step predictor and block arithmetic coding.

• Journal of Korea Multimedia Society
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• v.17 no.8
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• pp.953-960
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• 2014

In Shamir's (t,n)-threshold based secret image sharing schemes, there exists a problem that the secret image can be reconstructed when an arbitrary attacker becomes aware of t secret image pieces, or t participants are malicious collusion. It is because that utilizes linear combination polynomial arithmetic operation. In order to overcome the problem, we propose a secret image sharing scheme using matrix decomposition and adversary structure. In the proposed scheme, there is no reconstruction of the secret image even when an arbitrary attacker become aware of t secret image pieces. Also, we utilize a simple matrix decomposition operation in order to improve the security of the secret image. In experiments, we show that performances of embedding capacity and image distortion ratio of the proposed scheme are superior to previous schemes.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.302-303
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• 2010

본 논문에서는 고속으로 홀로그램을 생성하기 위해 새로운 컴퓨터 생성 홀로그램(computer-generated hologram, CGH) 수식을 제안하고, 셀 기반의 VLSI(very large scale integrated circuit) 구조를 제안하였다. 기본 CGH 수식에서 가로 또는 세로 방향의 연산 규칙을 찾아낸 후 가로 또는 세로 방향의 홀로그램 화소를 병렬적으로 구할 수 있는 수식을 유도하였다. 제안한 수식을 바탕으로 초기 파라미터 연산기(initial parameter calculator)와 업데이트-위상 연산기(update-phase calculator)로 구성된 CGH 셀의 구조를 제안하고 하드웨어로 구현하였다. 수식의 변형을 통해서 하드웨어를 간략화 시킬 수 있었고, CGH의 확장을 통해 가로 방향으로 병렬화시킬 수 있는 하드웨어 구조도 보였다. 실험에서는 하드웨어에 사용된 자원을 분석하였다. CGH 커널과 프로세서의 구조는 이전 연구에서 사용된 플랫폼을 그대로 사용하였다.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.837-840
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• 2005

This paper presents 3D graphics lighting processor based on vector processing using pipeline chaining. The lighting process of 3D graphics rendering contains many arithmetic operations and its complexity is very high. For high throughput, proposed processor uses pipelined functional units. To implement fully pipelined architecture, we have to use many functional units. Hence, the number of functional units is restricted. However, with the restricted number of pipelined functional units, the utilization of the units is reduced and a resource reservation problem is caused. To resolve these problems, the proposed architecture uses vector processing using pipeline chaining. Due to its pipeline chaining based architecture, it can perform 4.09M vertices per 1 second with 100MHz frequency. The proposed 3D graphics lighting processor is compatible with OpenGL ES API and the design is implemented and verified on FPGA.

• ETRI Journal
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• v.37 no.1
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• pp.107-117
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• 2015

This paper presents an energy-efficient (low power) prime-field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a $0.13{\mu}m$ standard CMOS technology, performs an 81-bit divisor multiplication in 503 ms consuming only $6.55{\mu}J$ of energy (average power consumption is $12.76{\mu}W$). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.991-994
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• 2006

최근 유비쿼터스와 관련하여 핵심 요소 기술로 활용되고 있는 ad-hoc네트워크와 소형 디바이스에 대한 연구가 활발히 진행되고 있다. 이중 소형 디바이스와 관련해 대표적인 기술이 RFID기술이다. RFID 기술의 특징은 주파수 통신을 이용하여 빠른 인식과 데이터 저장이 가능해 기존의 바코드 기술을 대체할수 있는 새로운 형태의 인증 기술이다. 그러나 RFID의 특성상 소형화된 하드웨어와 주파수 통신을 이용할 경우 보안상 많은 취약성이 존재할 수 있다. 따라서 본 논문에서는 기존의 RFID 기술을 분석한 뒤 보안적 취약성을 보완할 수 있는 등차수열을 이용한 안전하고 효율적인 RFID 인증 기술을 제안하고자 한다. 제안된 방식의 경우 등차수열을 이용함으로서 기존의 방식보다 연산량에 따른 효율성을 유지하면서 기존의 방식의 보안 취약성 보완할 수 있는 방식을 제안하고자 한다.

• Science of Emotion and Sensibility
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• v.4 no.1
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• pp.1-5
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• 2001

The evaluation of mental workload is measured by subjective ratings, physiological signals. It takes long time to analysis the measured signals and is very tedious and time-consumming work. Therefore, to evaluate the affect of workload effectively, real-time measurement system is required. In this paper, real-time mental workload measurement system using cardiac autonomic indiced which reflect well the mental workload was developed and evaluated. Analyzed indices were HR, IBI, Lorentz plot, CSI, CVI, and LF/HF ratio of heart rate variability. The system was applied to evaluate the affect of arithmetic task and showed good results. This system was consisted of ECG amplifier, A/D converter, and personal computer, and algorithm was implemented using LabVIEW.

• 제어로봇시스템학회:학술대회논문집
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• 1994.10a
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• pp.753-757
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• 1994

In control system design, whether the various subsystems are in discrete time or continuous time, the state space is usually regarded as a continuum. However, when the system is implemented, some subsystems may have a state space which is a subset of finite computer arithmetic. This is an important concern if a subsystem has chaotic behaviour, because it is theoretically possible for rich and varied motions in a continuum to collapse to trivial and degenerate behaviour in a finite and discrete state space [5]. This paper discusses new ways to describe these effects and reports on computer experiments which document and illustrate such collapsing behaviour.