• Journal of Information Processing Systems
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• v.13 no.2
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• pp.204-214
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• 2017

Artificial intelligence, especially deep learning technology, is penetrating the majority of research areas, including the field of bioinformatics. However, deep learning has some limitations, such as the complexity of parameter tuning, architecture design, and so forth. In this study, we analyze these issues and challenges in regards to its applications in bioinformatics, particularly genomic analysis and medical image analytics, and give the corresponding approaches and solutions. Although these solutions are mostly rule of thumb, they can effectively handle the issues connected to training learning machines. As such, we explore the tendency of deep learning technology by examining several directions, such as automation, scalability, individuality, mobility, integration, and intelligence warehousing.

• Journal of KIISE:Software and Applications
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• v.31 no.5
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• pp.632-642
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• 2004

The modern softwares have features of modularity and extensibility, and there are several researches on extensible programming languages and compilers. In this paper, we introduce Argos programming language, which provides the extensibility with the concept of plugin languages. A plugin language is used to define a method of a class, and the plugin language processors can be added and replaced dynamically The plugin languages may be used to support multiparadigm programming or domain specific languages.

• Electronics and Telecommunications Trends
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• v.33 no.4
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• pp.14-22
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• 2018

Deep neural networks (DNNs) are widely used in various domains such as speech and image recognition. DNN software frameworks such as Tensorflow and Caffe contributed to the popularity of DNN because of their easy programming environment. In addition, many companies are developing neuromorphic processing units (NPU) such as Tensor Processing Units (TPUs) and Graphical Processing Units (GPUs) to improve the performance of DNN processing. However, there is a large gap between NPUs and DNN software frameworks due to the lack of framework support for various NPUs. A bridge for the gap is a DNN software platform including DNN optimized compilers and DNN libraries. In this paper, we review the technical trends of DNN software platforms.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2388-2399
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• 2000

This paper describes a parallel programming environment to help programmers to write parallel programs. The parallel programming environment does lexical analysis and syntax analysis like front-end part of common compilers, data flow analysis and data dependence analysis for variables used in programs, and various program transformation methods for parallel programming. Especially, graphic user interface is provided for programmer to get parallel programs easily.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.40-46
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• 1990

This paper describes a design and an implementation of a machine-independent global optimizer which is a required module of RISC compiler system designs. It receives a triple as input and performs data flow analysis, common subexpression elimination and code motion and finally generates the optimized code. Since the implemented optimizer operates on the machine-independent intermediate code, its portability is good for many high level languages and target machines. It performs the effective optimizations to improve the execution time of programs.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.313-316
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• 2001

In this paper we present the design of a JPEG Encoder using SystemC Methodology Our methodology supports the efficient mapping of C/C++ functional descriptions directly into hardware. The use of C/C++ to model al1 parts of the system provides great flexibility and enables faster simulation compared to existing methodologies. The designer can estimate system performance and verify functional correctness of the designs using commonly available software compilers. A design flow in SystemC begins with an untimed description in C++, using a library of new data types useful for modeling hardware. The description can be compiled and simulated for functional correctness. Then, the design may be refined by adding interface specification and timing information, and again the timed description can be compiled with a standard C++ compiler, simulated, and debugged.

• Journal of the Korean Society for Library and Information Science
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• v.2
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• pp.79-102
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• 1971

The P'aerim and the Taedong Yasung are the two better known among unofficial history collections of the Yi Dynasty still available. The compilers and writers of unofficial historical records generally were people without official connection with the incidents recorded, and were thus in a position to be critical in their evaluation. Therefore, in order to gain a balanced view of Korean history, these unofficial history sources must also be consulted. However, there are differences in the contents of various unofficial history collections, even though the titles may be identical. For this reason, the writer has made a comparative study on the. contents of both the P'aerim and the Taedong Yasung. As a result, various differences between the two collections are noted. This points out the need for continued research on collections of unofficial historical records.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.28-37
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• 1996

Syntax notation one (ASN.1) defined by ITU-T and ISO, is a formal abstrct specification language which has been widely used in international standards specifiation to inteconnect distributed open systems. It si necessary to have well defined encoder/decoder modules which taranslate ASN.1 datum to BER octets stream to interconnect distributed open systems. In this paper, we designed and implemented a new ASN.1-to-C compiler, called HYASNC (hanyang ASN.1-to-C), which atutomatically translates and ASN.1-to-C compiler, called HYASNC (hanyang ASN.1-to-C), which automatically translates an ASN.1 specification into C-language BER encoders and decoders with simple and neat I/F for the defined ASN.1 data types, and enhanced BER (basic encoding rules)encoding/decoding libraries, called HY(hanyang)BER library, and useful utility functions. And this paper discusses HYASNC compiler, HY BER runtime library's design and implementation principles, and also evaluates the perfomrance of HY BER library and the interoperability with other ASN.1 compilers.

• The Journal of Information Technology
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• v.5 no.4
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• pp.35-44
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• 2002

The tradeoff of Java's portability is the inefficiency of interpretation. Also, the standard Java class library may not support the platform-dependent features needed by your application. Several solutions have been proposed to overcome these problems, such as JNI, JIT, off-line bytecode compilers. In this paper, we present an mixed-mode execution model which Java virtual machine executes together with native code. This execution model and its translator preserves the ability to dynamically load bytecode, and reduce the difficulties of JNI usages. Our system is more efficient than JIT, and helps programmer to write C implementation for the native method without the concept of JNI.

• Journal of Information Processing Systems
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• v.8 no.2
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• pp.331-346
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• 2012

Task-based programming is becoming the state-of-the-art method of choice for extracting the desired performance from multi-core chips. It expresses a program in terms of lightweight logical tasks rather than heavyweight threads. Intel Threading Building Blocks (TBB) is a task-based parallel programming paradigm for multi-core processors. The performance gain of this paradigm depends to a great extent on the efficiency of its parallel constructs. The parallel overheads incurred by parallel constructs determine the ability for creating large-scale parallel programs, especially in the case of fine-grain parallelism. This paper presents a study of TBB parallelization overheads. For this purpose, a TBB micro-benchmarks suite called TBBench has been developed. We use TBBench to evaluate the parallelization overheads of TBB on different multi-core machines and different compilers. We report in detail in this paper on the relative overheads and analyze the running results.