• Title/Summary/Keyword: Compensation Circuit

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Multi-Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

  • Mohammad Ali Bandari;Mohammad Bagher Tavakoli;Farbod Setoudeh;Massoud Dousti
    • ETRI Journal
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    • v.45 no.4
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    • pp.690-703
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    • 2023
  • Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 ㎛. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 ㎼.

A Novel Zero-Crossing Compensation Scheme for Fixed Off-Time Controlled High Power Factor AC-DC LED Drivers

  • Chang, Changyuan;Sun, Hailong;Zhu, Wenwen;Chen, Yao;Wang, Chenhao
    • Journal of Power Electronics
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    • v.16 no.5
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    • pp.1661-1668
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    • 2016
  • A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5μm 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

A Topological Transformation and Hierarchical Compensation Capacitor Control in Segmented On-road Charging System for Electrical Vehicles

  • Liu, Han;Tan, Linlin;Huang, Xueliang;Guo, Jinpeng;Yan, Changxin;Wang, Wei
    • Journal of Power Electronics
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    • v.16 no.4
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    • pp.1621-1628
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    • 2016
  • Experiencing power declines when the secondary coil is at the middle position between two primary coils is a serious problem in segmented on-road charging systems with a single energized segmented primary coil. In this paper, the topological transformation of a primary circuit and a hierarchical compensation capacitor control are proposed. Firstly, the corresponding compensation capacitors and receiving powers of different primary structures are deduced under the condition of a fixed frequency. Then the receiving power characteristics as a function of the position variations in systems with a single energized segmented primary coil and those with double segmented primary coils are analyzed comparatively. A topological transformation of the primary circuit and hierarchical compensation capacitor control are further introduced to solve the foregoing problem. Finally, an experimental prototype with the proposed topological transformation and hierarchical compensation capacitor control is carried out. Measured results show that the receiving power is a lot more stable in the movement of the secondary coil. It is a remarkable fact that the receiving power rises from 10.8W to 19.2W at the middle position between the two primary coils. The experimental are in agreement with the theoretical analysis.

Ku-Band Power Amplifier MMIC Chipset with On-Chip Active Gate Bias Circuit

  • Noh, Youn-Sub;Chang, Dong-Pil;Yom, In-Bok
    • ETRI Journal
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    • v.31 no.3
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    • pp.247-253
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    • 2009
  • We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 ${\mu}m$ GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.

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Miniaturized Sensor Interface Circuit for Respiration Detection System (호흡 검출 시스템을 위한 초소형 센서 인터페이스 회로)

  • Jo, Sung-Hun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.8
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    • pp.1130-1133
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    • 2021
  • In this paper, a miniaturized sensor interface circuit for the respiration detection system is proposed. Respiratory diagnosis is one of the main ways to predict various diseases. The proposed system consists of respiration detection sensor, temperature sensor, and interface circuits. Electrochemical type gas sensor using solid electrolytes is adopted for respiration detection. Proposed system performs sensing, amplification, analog-to-digital conversion, digital signal processing, and i2c communication. And also proposed system has a small form factor and low-cost characteristics through optimization and miniaturization of the circuit structure. Moreover, technique for sensor degradation compensation is introduced to obtain high accuracy. The size of proposed system is about 1.36 cm2.

Charge Injection 보상 회로의 비교

  • 박상훈;김수은;박홍준
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.141-144
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    • 2002
  • Several charge Injection compensation circuits, such as, the dummy transistor circuit, the switched OP-amp circuit, the switched capacitor circuit, were fabricated and the test results were compared. The differences between SPICE simulation results and measurements were within around 10%.

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A Convergence Compensation Algorithm for A CRT Projection TV (CRT 프로젝션 TV에서의 Convergence 보정 알고리즘)

  • 강석판;정창기;최두현
    • Proceedings of the IEEK Conference
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    • 2003.11a
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    • pp.355-358
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    • 2003
  • Basically, the mis-convergence, which is inevitable in CRT Projection TV. is the degree of deviation of red and blue from green beam. The cause of mis-convergence is the change of magnetic field and electrical characteristic in deflection circuits and convergence amplification circuit. A new and easily implementable mis-convergence compensation algorithm is presented in this paper. The proposed algorithm does not needs any compensation devices. It uses only TV OSD and a remote controller and anyone who wants to compensate can easily correct the mismatch. Through real compensation experiments, it is found that the proposed algorithm is useful and effective one.

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A Study on Reactive Current Compensation Using Thyristor Switch (Thyristor Switch를 사용한 무효전류 보상에 관한 연구)

  • 박민호;이복용
    • 전기의세계
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    • v.28 no.12
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    • pp.41-45
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    • 1979
  • Improvement of power factor is achieved by reactive-current compensation, connecting power condenser to the circuit. This paper describes a method of reactive-current compensation, employing thyristor switching of capacitor banks without any breaker. This method reduces supply transients to the minimum by means of connecting condenser, because thyristor is triggered at zero point in condenser current. The reactive current detection and the experimental system to trigger thyristor at appropriate moment are given. IThe results show the fast reactive-current compensation on the condition of minimum transient.

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Grid Peak Power Limiting / Compensation Power Circuit for Power Unit under Dynamic Load Profile Conditions (Dynamic Load Profile 조건의 전원 장치에 있어서 계통 Peak Power 제한/보상 전력 회로)

  • Jeong, Hee-Seong;Park, Do-Il;Lee, Yong-Hwi;Lee, Chang-Hyeon;Rho, Chung-Wook
    • The Transactions of the Korean Institute of Power Electronics
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    • v.27 no.5
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    • pp.376-383
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    • 2022
  • The improved performance of computer parts, such as graphic card, CPU, and main board, has led to the need for power supplies with a high power output. The dynamic load profile rapidly changes the usage of power consumption depending on load operations, such as PC power and air conditioner. Under dynamic load profile conditions, power consumption can be classified into maximum, normal, and standby power. Several problems arise in the case of maximum power. Peak power is generated at the system power source in the maximum-power situation. Frequent generation of peak power can cause high-frequency problems and reduce the life of high-pressure parts (especially high-pressure capacitors). For example, when a plurality of PCs are used, system overload occurs due to peak power generation and causes problems, such as power failure and increase in electricity bills due to exceeded contract power. To solve this problem, a system peak power limit/compensation power circuit is proposed for a power supply under dynamic load profile conditions. The proposed circuit detects the system current to determine the power situation of the load. When the system current is higher than the set level, the circuit recognizes that the system current generates peak power and compensates for the load power through a converter using a super capacitor as the power source. Thus, the peak power of loads with a dynamic load profile is limited and compensated for, and problems, such as high-frequency issues, are solved. In addition, the life of high-pressure parts is increased.