• Proceedings of the Optical Society of Korea Conference
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• 2009.02a
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• pp.293-294
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• 2009

The spectral responsivity of solar cells has been measured under high background irradiance using an LED-based differential spectral responsivity Comparator (DSR-C). The comparator developed is fully automated and has some advantages: It does not need a chopper to modulate the light. Unlike the conventional method, it does not require a monochromator to select wavelength. It covers a wavelength range up to 1200 nm. The wavelength range of the comparator is limited by the spectral power distribution of the LEDs and the spectral responsivity of the standard detector. An active temperature control was utilized to meet the specified standard conditions of solar cell test. This work shows the effect of different levels of background irradiance on the spectral responsivity and the importance of same background irradiance for solar cell test as specified by the corresponding standard.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.926-932
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• 2007

A recently developed methods for on-site calibration of the current transformer (CT) comparator system have been reviewed in the paper. The method utilizes several traveling standards, which consist of the CT, non-reactive standard resistors, wide ratio error CT, and shunt resistors. The traveling CT is used for absolute evaluation of a standard CT belonging to industry. The non-reactive standard resistors and a wide ratio error CT are used for the linearity check of errors in the current comparator. The shunt resistors are used for evaluation of CT burden of industry.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.7
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• pp.1268-1274
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• 2007

A recently developed methods for the on-site calibration of the voltage transformer (VT) comparator system have been reviewed in the paper. The method utilizes the several traveling standards consisting of the VT, the non-reactive standard resistors, the wide ratio error VT, and the decade resistors. The VT is used for the absolute evaluation of a standard VT belonging to the industry. The non-reactive standard resistor and wide ratio error VT are used for the linearity check of errors in the voltage comparator of the industry. The decade resistors are used for evaluation of a VT burden of the industry.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.279-284
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• 2008

We have developed two absolute evaluation technology of inductor using current transformer (CT) comparator. One is the method that the reactance of inductor is obtained by analysing the equivalent circuit of CT with inductor connected to series at secondary terminal of CT. The other is the method that the reactance of inductor is obtained by comparing phase displacement of current flowing on inductor by using CT comparator. These technologies have the advantage to apply up to rated current and voltage of inductor. The method was applied to inductors under test in the range of $100 {\mu}H{\sim}1\;H$. The inductance of the inductor under test obtained in this study are consistent with those measured by LCR meter using the same inductor within an expanded uncertainty (k = 2) in the overall range of inductance.

• Proceedings of the Korean Magnestics Society Conference
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• 2005.06a
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• pp.204-205
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• 2005

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1091-1097
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• 2013

This paper presents a rectifier with comparator using unbalanced body biasing in $0.11{\mu}m$ RF CMOS process. It is composed of MOSFETs and two comparators. The comparator is used to reduce reverse leakage current which occurs when the load voltage is higher than input voltage. For the comparator, unbalanced body biasing is devised. By using unbalanced body biasing, reference voltage for comparator changing from high state to low state is increased, and it reduces time interval for leakage current to flow. 13.56 MHz 2 Vpp signal is used for input and $1k{\Omega}$ resistor and 1 nF capacitor are used for output load for simulation and experimental environment. In simulation environment, voltage conversion efficiency(VCE) is 87.5 % and Power conversion efficiency(PCE) is 50 %. When the rectifier is measured, VCE shows 90.203 % and PCE shows 45 %.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1050-1052
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• 1987

This study presents mental model based on cognitive psychology and deals with implementation of associative comparator using learning automata with random access memories.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1250-1259
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• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• Journal of IKEEE
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• v.16 no.1
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• pp.20-27
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• 2012

In order to overcome jamming, a hysteresis tunable monolithic comparator circuit based on a 0.35 ${\mu}m$ CMOS process is suggested, designed, fabricated, measured and analyzed in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. An improved variable hysteresis comparator circuit controlled by serial digital bits is suggested, designed and simulated to overcome jamming in modern warfare.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.483-485
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• 2010

A 200kS/s 10-bit successive approximation(SA) ADC with a rail-to-rail input range is proposed. The proposed SA ADC consists of DAC, comparator, and successive approximation register(SAR) logic. The folded-type capacitor DAC with the boosted NMOS switches is used to reduce the power consumption and chip area. Also, the time-domain comparator which uses a fully differential voltage-to-time converter improves the PSRR and CMRR. The SAR logic uses the flip-flop with a half valid window, it results in the reduction of the power consumption and chip area. The proposed SA ADC is designed by using a $0.18{\mu}m$ CMOS process with 1V supply.