• Journal of the Society of Naval Architects of Korea
• /
• v.60 no.1
• /
• pp.48-56
• /
• 2023

This paper implements many-to-many communication between users and develops a multi-functional smart helmet for worker protection and environmental safety in the shipbuilding and shipping industry. First, the communication situation is recorded in the field to perform signal processing for noise that interferes with communication. Then, it deals with the contents of developing smart helmets, data acquisition, algorithms, and simulations. The simulation results analyzed by applying the adaptive algorithm are shown, and their usefulness is confirmed. In conclusion, looking at the optimization process for the convergence factor of the Least Mean Square and Filtered-x Least Mean Square Adaptation Algorithm was possible. It is thought that it has laid the foundation for implementing many-to-many communication, the function of smart helmets that reduces or removes various noises at the shipyard in the future.

• Journal of the Korea Society of Computer and Information
• /
• v.25 no.1
• /
• pp.1-11
• /
• 2020

In this paper, we present a technique that executes MPI parallel programs, that are developed on processor-centric computer architecture, more efficiently on memory-centric computer architecture without program modification. The technique we present here improves performance by replacing low-speed data communication over the network of MPI library functions with high-speed data communication using the property called fast large shared memory of memory-centric computer architecture. The technique we present in the paper is implemented in two programs. The first program is a modified MPI library called MC-MPI-LIB that runs MPI parallel programs more efficiently on memory-centric computer architecture preserving the semantics of MPI library functions. The second program is a simulation program called MC-MPI-SIM that simulates the performance of memory-centric computer architecture on processor-centric computer architecture. We developed and tested the programs on distributed systems environment deployed on Docker based virtualization. We analyzed the performance of several MPI parallel programs and showed that we achieved better performance on memory-centric computer architecture. Especially we could see very high performance on the MPI parallel programs with high communication overhead.

• Journal of information and communication convergence engineering
• /
• v.17 no.2
• /
• pp.117-127
• /
• 2019

In software engineering, to ensure reliability between systems, describing both system architecture and assurance arguments between system elements is considered necessary. There are proposals for system architecture assurance, but use of these traditional methods often requires development of different diagrams using different editors. Because the visual sense of the traditional methods is inadequate, errors readily occur when manipulating different diagrams. Therefore, it is essential that the assurance of dependability between components and systems is visualized and easy to understand. In this paper, an integrated approach to describe the relationship between system actors and system architecture is proposed, and this approach is clarified using an enterprise architecture modeling language. A case study is carried out and comparison to the traditional approach $d^*$ framework is explained. The comparison results show that the proposed approach is more suitable for ensuring dependability in system architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.101-111
• /
• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• 제어로봇시스템학회:학술대회논문집
• /
• 2004.08a
• /
• pp.1732-1737
• /
• 2004

This paper proposes Internet-based checking technique for machine-tools with variant CNC (Computerized Numerical Controller). According to the architecture of CNC, CNC is classified into two types such as CAC (Closed Architecture Controller) which is conventional CNC, and OAC (Open Architecture Controller) which is a recently introduced PC-based controller. CAC has a closed architecture and it is dependent on CNC vender specification. Because of this, it has been very difficult for users to implement an application programs in CNC domain. Therefore, an additionally special module is required for Internet-based application such as remote checking. In this case, web I/O embedded module can be efficiently applied for Internet-based checking. The module is directly attached to TCP/IP network for communication. In order to obtain the monitoring data of CNC machines, the I/O signals of the module are assigned to PLC (Programmable Logic Controller) input and output (I/O) signals within CNC domain. On the other hand, OAC has a PC-based open architecture and an additional module is not necessary for the connection with external site. Because of this, a simple DAU is just used for signal sensing and data acquisition without additional communication modules. For Internet-based remote checking of machine-tools with OAC, a user-defined daemon and application programs are implemented as the form of internal function within the PC-based controller. Internet communication is performed between the daemon program in CNC domain and web script programs in external server. Checking points defined in this research are classified into two categories such as structured point and operational point. The formal includes the vibration of bearing, temperature of spindle unit and another periodical management. And the latter includes oil checking, clamp locking/unlocking and machining on/off status.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.6
• /
• pp.1449-1454
• /
• 2015

Virtualization lacks capabilities for enabling the application to scale efficiently because of new applications components which are raised to be configured on demand. In this paper, we propose an architecture that affords mobile app based on nomadic smartphone using not only mobile cloud computing-cloudlet architecture but also a dedicated platform that relies on using virtual private mobile networks to provide reliable connectivity through LTE(Long Term Evolution) wireless communication. The design architecture lies with how the cloudlet host discovers service and sends out the cloudlet IP and port while locating the user mobile device. We demonstrate the effectiveness of the proposed architecture by implementing an android application responsible of real time analysis by using a vehicle to applications smartphone interface approach that considers the smartphone to act as a remote users which passes driver inputs and delivers outputs from external applications.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.19 no.8
• /
• pp.19-24
• /
• 2018

The IP Multimedia Subsystem(IMS) is an architectural framework for delivering IP multimedia services to mobile users. In order to guarantee the reliability and Quality of Service(QoS) of a variety of multimedia services, we need a new evolutionary approach that maintains the IMS based signaling platform which can perform the processing of flow through distributed controllers. Software Defined Network(SDN) is an architecture purporting to be distributed, dynamic, cost-effectives as well as adapting and seeking to be suitable for the high-bandwidth, dynamic nature of today's applications. It requires some methods for the control plane to communication with the data plane. One of such mechanisms is OpenFlow which is a prominent standard protocol and interface that is responsible for managing the network resources by using the remote SDN controller. In this paper, we propose a straightforward approach for integrating SDN technology together with the IMS architecture. Therefore we propose and construct a combined architecture model that performs flow processing using OpenFlow via the IMS based signaling platform, which maintains the existing telecom call service. Additionally, we describe some relevant experimentation results from the proposed architecture.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.140-148
• /
• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.4 no.6
• /
• pp.1294-1310
• /
• 2010

User authentication using fingerprint information provides convenience as well as strong security. However, serious problems may occur if fingerprint information stored for user authentication is used illegally by a different person since it cannot be changed freely as a password due to a limited number of fingers. Recently, research in fuzzy fingerprint vault system has been carried out actively to safely protect fingerprint information in a fingerprint authentication system. In addition, research to solve the fingerprint alignment problem by applying a geometric hashing technique has also been carried out. In this paper, we propose the hardware architecture for a geometric hashing based fuzzy fingerprint vault system that consists of the software module and hardware module. The hardware module performs the matching for the transformed minutiae in the enrollment hash table and verification hash table. On the other hand, the software module is responsible for hardware feature extraction. We also propose the hardware architecture which parallel processing technique is applied for high speed processing. Based on the experimental results, we confirmed that execution time for the proposed hardware architecture was 0.24 second when number of real minutiae was 36 and number of chaff minutiae was 200, whereas that of the software solution was 1.13 second. For the same condition, execution time of the hardware architecture which parallel processing technique was applied was 0.01 second. Note that the proposed hardware architecture can achieve a speed-up of close to 100 times compared to a software based solution.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.1
• /
• pp.169-177
• /
• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.