• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.10
• /
• pp.964-970
• /
• 2013

This paper presents a bandpass wireless 3-D chip to chip interface technique. The proposed technique uses direct amplitude modulation of the free running oscillator which especially utilizes the coupling capacitance between two stacked chips as a part of the resonator. Therefore, the oscillator is three dimensionally configured and a simple envelope detector can be used as a receiver without any additional matching circuitry. The proposed link was designed and fabricated using 110 nm CMOS technology and experimental results successfully showed the data transmission at a data rate of 2 Gb/s for the stacked chips with a thickness of 50 ${\mu}m$ consuming 4.32 mW. The sizes of the Tx and Rx chips are 0.045 $mm^2$ and 0.029 $mm^2$, respectively.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.3
• /
• pp.49-59
• /
• 2001

Wireless communication systems will be one of the biggest drivers of semiconductor products over the next decade. Global Positioning System (GPS) and Blue-tooth, HomeRF, and Wireless-LNA system are just a few of RF-module candidate awaiting integration into next generation mobile phone. Motivated by the growing needs for lowcost and multi-band/multi-function single chip wireless transceivers, CMOS technology has been recognized as a most promising candidate for the implementation of the future wireless communication systems. This paper presents recent developments in RF CMOS technology so far, much of them have been developed in ETRI, and from them forecasts technology trends in the near future.

• Proceedings of the KIPE Conference
• /
• 2008.06a
• /
• pp.345-347
• /
• 2008

실제 휴대폰 환경에서 쓰이고 있는 전력 시스템이 어떻게 되어 있는지 고찰해보고, 어떤 것들이 문제가 되고 있으며, 그 해결방안으로는 어떤 것들이 있는지 알아본다. 각 regulator의 정의와 그 spec에 대하여 장단점 분석과 함께 실무적으로 어떻게 응용되고 있으며 미래의 발전방향은 어떻게 될 것인지 고찰한다. SoC(System on Chip)의 결정체인 휴대폰에서 전력 시스템 디자인이 차지하는 그 영향에 대해 논하고 그 application 관점에서 체크리스트를 만들어보기로 한다.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.199-202
• /
• 1999

In this paper, a possibility of building various types of RF passive components using the silicon micromachining technique has been examined with special emphasis on the wireless and mobile communication applications. Silicon micromachining technique is compatible with conventional silicon IC process and could provide a possibility of integrating base-band signal processing units and RF passive and active circuit components all in one silicon wafer rendering implementation of system-on-chip paradigm for future mobile and wireless communication systems.

• The Magazine of the IEIE
• /
• v.29 no.9
• /
• pp.1020-1020
• /
• 2002

Wireless communication systems will be one of the biggest drivers of semiconductor products over the next decade. Global Positioning System (GPS) and Blue-tooth, HomeRF, and Wireless-LNA system are just a few of RF-module candidate awaiting integration into next generation mobile phone. Motivated by the growing needs for low-cost and multi-band/multi-function single chip wireless transceivers, CMOS technology has been recognized as a most promising candidate for the implementation of the future wireless communication systems. This paper presents recent developments in RF CMOS technology, which is classified into device technology and circuit technology and from them forecasts technology trends in the near future.

• The Magazine of the IEIE
• /
• v.29 no.9
• /
• pp.18-30
• /
• 2002

Wireless communication systems will be one of the biggest drivers of semiconductor products over the next decade. Global Positioning System (GPS) and Blue-tooth, HomeRF, and Wireless-LNA system are just a few of RF-module candidate awaiting integration into next generation mobile phone. Motivated by the generation mobile phone. Motivated by the growing needs for low-cost and multi-band/multi-function single chip wireless transceivers, CMOS technology has been recognized as a most promising candidate for the implementation of the future wireless communication systems. This paper presents recent developments in RF CMOS technology, which is classified into device technology and circuit technology and from them forecasts technology and from them forecasts technology trends in the near future.

• Proceedings of the IEEK Conference
• /
• 2001.06e
• /
• pp.157-160
• /
• 2001

We studied about the lighting control system on pc using PLM(Power Line Modem). The PLM is composed of FSK IC-chip and the circuit for the power line communication. We developed the control program using visual c++ language on PC for dimming the lamps. In this paper dimming controller was made with PIC161F874 and its communication speed was 1200 boad rates.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.09a
• /
• pp.65-89
• /
• 2003

Next Highly sophisticated communication generation of the Advanced Electronics and Imaging processing society will require a vast information volume and super high speed signal transport and information instruction. This means that super high technology should be created for satisfying the demand. It's also required the high reliability of the communication system itself, It will be supported the new advanced packaging technology of the 3 Dimensional structured system and system integration technology. Here is introduced the new 3 Dimensional technology for IC nnd LSI packaging and Opt-electronics Packaging of ASET activity in Japan.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.8
• /
• pp.66-75
• /
• 2016

Due to aggressive scaling of device sizes and reduced noise margins, physical defects caused by aging and process variation are continuously increasing. Additionally, with scaling limitation of metal wire and the increasing of communication volume, fault tolerant method in manycore network-on-chip (NoC) has been actively researched. However, there are few researches investigating reliability in NoC with voltage-frequency-island (VFI) regime. In this paper, we propose a table-based routing technique that can communicate, even if link failures occur in the VFI NoC. The output port is alternatively selected between best and the detour routing path in order to improve reliability with minimized hardware cost. Experimental results show that the proposed method achieves full coverage within 1% faulty links. Compared to $d^2$-LBDR that also considers a routing method for searching a detour path in real time, the proposed method, on average, produces 0.8% savings in execution time and 15.9% savings in energy consumption.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.29 no.10
• /
• pp.758-765
• /
• 2018

This paper presents a 24-GHz frequency-modulated continuous wave(FMCW) radar transceiver with two Rx and one Tx channels in 65-nm complementary metal-oxide-semiconductor(CMOS) process and implemented it on a radar system using the developed transceiver chip. The transceiver chip includes a $14{\times}$ frequency multiplier, low-noise amplifier, down-conversion mixer, and power amplifier(PA). The transmitter achieves >10 dBm output power from 23.8 to 24.36 GHz and the phase noise is -97.3 GHz/Hz at a 1-MHz offset. The receiver achieves 25.2 dB conversion gain and output $P_{1dB}$ of -31.7 dBm. The transceiver consumes 295 mW of power and occupies an area of $1.63{\times}1.6mm^2$. The radar system is fabricated on a low-loss Duroid printed circuit board(PCB) stacked on the low-cost FR4 PCBs. The chip and antenna are placed on the Duroid PCB with interconnects and bias, gain blocks and FMCW signal-generating circuitry are mounted on the FR4 PCB. The transmit antenna is a $4{\times}4$ patch array with 14.76 dBi gain and receiving antennas are two $4{\times}2$ patch antennas with a gain of 11.77 dBi. The operation of the radar is evaluated and confirmed by detecting the range and azimuthal angle of the corner reflectors.