• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.714-723
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• 2003

An effective technique to increase the signal swing and reduce noise is to use fully-differential -circuits. However, design of a common-mode feedback (CMFB) circuit that stabilizes the common-mode output level is essential. In this paper, a general description is given to fully-differential amplifiers with their CMFB loops, then a new error amplifier that is just composed of transistors and stabilizes the DC output level is proposed. We designed a simple and efficient bias circuit that allows the stability and maximum input swing. Simulation result shows the enhanced phase margin and increased differential-mode input swing with a proposed error amplifier.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.479-482
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• 1993

A fully balanced differential amplifier can achieve high-gain wide-bandwidth characteristics. And also, Offset PSRR, CMRR and Noise performance of that are excellent, but these merits can be achieved only when the architecture holds fully balanced. Commonly, the fully balanced differential amplifier has a common mode feedback(CMFB) circuit in order to maintain the balance. This paper presents improved characteristics of the CMFB circuit and designs the wide-bandwidth CMOS Op-amp. The unity gain bandwidth of this Op-amp is 50MHz with the load capacitor 2pF, and the value of phase margin is $85^{\circ}$.

• 한국ITS학회:학술대회논문집
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• v.2006 no.10
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• pp.312-315
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• 2006

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.81-88
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• 2006

This paper describes a new linear operational transconductance amplifier (OTA). To improve the linearity of the OTA, we employ a mobility compensation circuit that combines the transistor paths operating at the triode and subthreshold regions. The common-mode control schemes consist of a common-mode feedback (CMFB) and common-mode feedforward (CMFF). The circuit enhances linearity of the transconductance (Gm) under the wide input voltage swing range. The proposed OTA shows ${\pm}1%$ Gm variation and the total harmonic distortion (THD) of below -73dB under the input voltage swing range of ${\pm}1.1V$. The OTA is implemented using a $0.35{\mu}m$ n-well CMOS process under 3.3V supply.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.348-351
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• 2001

In this paper, the Gm-C filter for low voltage and low power applications using a fully-differential transconductor is presented. The designed transconductor using the series composite transistors and the low voltage composite transistors has wide input range at low supply voltage. A negative resistor load (NRL) technology for high DC gain of the transconductor is employed with a common mode feedback(CMFB). As a design example, the third-order Elliptic lowpass filter is designed. The designed filter is simulated and examined by HSPICE using TSMC $0.35{\mu}m$ CMOS n-well parameters. The simulation results show 138kHz cutoff frequency and 11.05mW power dissipation with a 3.3V supply voltage.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.257-260
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• 2000

In this paper, a Gm-C filter for low voltage and low power applications using a fully-differential transconductor is presented. The designed transconductor using the series composite transistors and the low voltage composite transistors has wide input range at low supply voltage. A negative resistor load (NRL) technology for high DC gain of the transconductor is employed with a common mode feedback (CMFB). As a design example, the third-order Elliptic lowpass filter is designed. The designed filter is simulated and examined by HSPICE using 0.25${\mu}{\textrm}{m}$ CMOS n-well parameters. The simulation results show 105MHz cutoff frequency and 2.4㎽ power dissipation with a 2.5V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.