• Smart Media Journal
• /
• v.4 no.2
• /
• pp.55-61
• /
• 2015

A bandwidth-enhanced ultra-wide band (UWB) CMOS balun-LNA is implemented as a part of a software defined radio (SDR) receiver which supports multi-band and multi-standard. The proposed balun-LNA is composed of a single-to-differential converter, a differential-to-single voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband balun-LNA exploiting negative feedback is implemented. By adopting a source follower-based inductive shunt peaking, the proposed balun-LNA achieves a wider gain bandwidth. Two LNA design examples are presented to demonstrate the usefulness of the proposed approach. The LNA I adopts the CS amplifier with a common gate common source (CGCS) balun load as the S-to-D converter for high gain and low noise figure (NF) and the LNA II uses the differential amplifier with the ac-grounded second input terminal as the S-to-D converter for high second-order input-referred intercept point (IIP2). The 3 dB gain bandwidth of the proposed balun-LNA (LNA I) is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average power gain of 18 dB and an IIP3 of -8 ~ -2 dBm are obtained. In simulation, IIP2 of the LNA II is at least 5 dB higher than that of the LNA I with same power consumption.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.9
• /
• pp.900-905
• /
• 2009

A common drain feedback CMOS wideband LNA with current bleeding and input inductive series-peaking techniques is presented in this paper. DC coupling is adopted between cascode and feedback amplifiers, so that the gain and NF of the LNA can be dynamically controlled by adjusting the bleeding current. The fabricated LNA shows the bandwidth of 2.5 GHz. The high gain mode shows 17.5 dB gain with $1.7{\sim}2.8\;dB$ NF and consumes 27 mW power and the low gain mode has 14 dB gain with $2.7{\sim}4.0\;dB$ NF and dissipates 1.8 mW from 1.8 V supply.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.4
• /
• pp.25-35
• /
• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2000.11a
• /
• pp.229-232
• /
• 2000

In this study, An active band grass filter for 2.14GHz have been designed with MMIC using negative resistance circuit. The negative resistance element was realized with a common-drain FET with series inductive feedback. The designed active filter showed an insertion loss of 0dB at 2.14GHz and a 3-dB bandwidth of 125MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.10
• /
• pp.1169-1176
• /
• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.