• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.8-8
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• 1995

• Korean Journal of Materials Research
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• v.12 no.11
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• pp.865-869
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• 2002

We investigated the reaction stability of titanium, cobalt and their bilayer films with side-wall spacer materials of SiO$_2$ for the salicide process. We prepared Ti 350 $\AA$, Co 150 $\AA$, Co 150 $\AA$/Ti 100 $\AA$ and Ti 100 $\AA$/Co 150 $\AA$ films on 1000 $\AA$-thick thermally grown SiO$_2$ substrates, respectively. Then the samples were rapid thermal annealed at the temperatures of $500^{\circ}C$, $600^{\circ}C$, and $700^{\circ}C$ for 20 seconds. We characterized the sheet resistance of the metallic layers with a four-point probe, surface roughness with scanning probe microscope, residual phases with an Auger depth profilometer, phase identification with a X-ray diffractometer, and cross-sectional microstructure evolution with a transmission electron microscope, respectively. We report that Ti reacted with silicon dioxide spacers above $700^{\circ}C$, Co agglomerated at $600^{\circ}C$, and Co/Ti, Ti/Co formed CoTi compound requiring a special wet process.

• Korean Journal of Materials Research
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• v.13 no.11
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• pp.711-716
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• 2003

Gate length, height, and silicide thickness have all been shrinking linearly as device density has progressively increased over the years. We investigated the effect of the cobalt diffusion during the silicide formation process on the 60$\AA$-thick gate oxide lying underneath the Ti/Co and Co/Ti bilayers. We prepared four different cobalt silicides, which have similar sheet resistance, made from the film structure of Co/Ti(interlayer), and Ti(capping layer)/Co, and peformed the current-voltage, time-to-break down, and capacitance-voltage measurements. Our result revealed that the cobalt silicide process without the Ti capping layer allowed cobalt atoms to diffuse into the upper interface of gate oxides. We propose that 100$\AA$-thick titanium interlayer may lessen the diffusion of cobalt to gate oxides in 1500-$\AA$ height polysilicon gates.

• Korean Journal of Materials Research
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• v.8 no.5
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• pp.470-473
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• 1998

$As^+$ was ion-implanted onto $CoSi_{2}$ thin films formed by rapidly thermal-annealed Co/Ti bilayers. Then the specimens were drive-in annealed at 500~100$0^{\circ}C$ to form ultra-shallow $n^+$p junction diodes and to measure their 1- V characteristics. When drive-in annealed at 50$0^{\circ}C$ for 280 sec., 50 nm thick ultra-shallow junctions were formed and di¬odes showed the best 1- V characteristics with low leakage current. In particular. the leakage current was 2 orders lower than that of diodes formed by using Co monolayer. It was attributed to uniform $CoSi_{2}$/Si interfaces.

• Korean Journal of Materials Research
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• v.9 no.11
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• pp.1117-1122
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• 1999

Amorphous Si and Co/Ti bilayers were sequentially evaporated onto 5- 10nm thick $\textrm{CoSi}_{2}$ and rapidly thermal-annealed(RTA) to form Co-polycide electrodes. Then, MOS capacitors were fabricated by doping poly-Si using SADS method. The C-V and leakage-current characteristics of the capacitors depending upon the RTA conditions were measured to study the effects of thermal stability of $\textrm{CoSi}_{2}$ and dopant redistribution on electrical properties of Co -polycide gates. Capacitors RTAed at $700^{\circ}C$ for 60-80 sec., showed excellent C-V and leakage-current characteristics due to degenate doping of poly-Si layers. But for longer time or at higher temperature, their electrical properties were degraeded due to $\textrm{CoSi}_{2}$ decomposition and subsequent Co diffusion. When making Co-polycide gate electrodes by SADS, not only degenerate doping of poly-Si layer. but also suppression of have been shown to be very critical.