• The KIPS Transactions:PartD
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• v.16D no.6
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• pp.825-834
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• 2009

최근에 낸드 플래시 메모리는 빠른 접근속도, 저 전력 소모, 높은 내구성 등의 특성으로 인하여 차세대 대용량 저장 매체로 각광 받고 있다. 그러나 디스크 기반의 저장 장치와는 달리 비대칭적인 읽기, 쓰기, 소거 연산의 처리 속도를 가지고 있고 제자리 갱신이 불가능한 특성을 가지고 있다. 따라서 디스크 기반 시스템의 버퍼 교체 정책은 플래시 메모리 기반의 시스템에서 좋은 성능을 보이지 않을 수 있다. 이러한 문제를 해결하기 위해 플래시 메모리의 특성을 고려한 새로운 플래시 메모리 기반의 버퍼 교체 정책이 제안되어 왔다. 본 논문에서는 디스크 기반의 저장 장치에서 우수한 성능을 보인 CLOCK-Pro를 낸드 플래시 메모리의 특성을 고려하여 개선한 CLOCK-NAND를 제안한다. CLOCK-NAND는 CLOCK-Pro의 알고리즘에 기반하며, 추가적으로 페이지 접근 정보를 효율적으로 활용하기 위한 새로운 핫 페이지 변경을 한다. 또한, 더티인 핫 페이지에 대해 콜드 변경 지연 정책을 사용하여 쓰기 연산을 지연하며, 이러한 새로운 정책들로 인하여 낸드 플래시 메모리에서 쓰기 연산 횟수를 효율적으로 줄이는 우수한 성능을 보인다.

• ETRI Journal
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• v.45 no.3
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• pp.534-542
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• 2023

The large amount of secondary effects in complementary metal-oxide-semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.9
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• pp.1652-1659
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• 2008

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.4 no.2
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• pp.29-36
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• 2005

All-optical fiber-type $2{\times}32$ splitters for an Ethernet PON (passive optical network) were fabricated by using a FBT (fiber biconical tapered) process and the performance of the splitters was tested in upstream transmission of the EPON system. The $2{\times}32$ splitters was obtained by cascading $1{\times}4$ splitters fabricated by a conventional FBT process and showed -18 dB of insertion loss with 1.5 dB uniformity of output power at each channel and -0.1 dB of polarization dependent loss. The insertion loss variation was below 0.1 dB at the temperature range of $-40^{\circ}C\;to\;80^{\circ}C$. For upstream channel transmission test in the EPON system were a Zig board and a burst mode receiver. Zenko-made optical module was used for the burst mode receiver by adding functions of serializer/deserializer and clock data recovery, a Virtex II pro20 chipset and Vitesse VSC7123 were used in the Zig board for characterizing the burst mode and in the clock data recovery chipset, respectively. Startup acquisition lock time and data acquisition lock time were measured to be 670ns and 400ns, respectively, in the upstream channel transmission of the EPON system adapting the $2{\times}32$ splitter fabricated in this work.

• The Korean Journal of Physiology and Pharmacology
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• v.26 no.6
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• pp.415-425
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• 2022

Memory formation in the hippocampus is formed and maintained by circadian clock genes during sleep. Sleep deprivation (SD) can lead to memory impairment and neuroinflammation, and there remains no effective pharmacological treatment for these effects. Myricetin (MYR) is a common natural flavonoid that has various pharmacological activities. In this study, we investigated the effects of MYR on memory impairment, neuroinflammation, and neurotrophic factors in sleep-deprived rats. We analyzed SD-induced cognitive and spatial memory, as well as pro-inflammatory cytokine levels during SD. SD model rats were intraperitoneally injected with 10 and 20 mg/kg/day MYR for 14 days. MYR administration significantly ameliorated SD-induced cognitive and spatial memory deficits; it also attenuated the SD-induced inflammatory response associated with nuclear factor kappa B activation in the hippocampus. In addition, MYR enhanced the mRNA expression of brain-derived neurotropic factor (BDNF) in the hippocampus. Our results showed that MYR improved memory impairment by means of anti-inflammatory activity and appropriate regulation of BDNF expression. Our findings suggest that MYR is a potential functional ingredient that protects cognitive function from SD.

• Molecules and Cells
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• v.41 no.8
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• pp.742-752
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• 2018

Parkinson's disease (PD) is a neurodegenerative disease characterized by progressive degeneration of dopaminergic (DAergic) neurons, particularly in the substantia nigra (SN). Although circadian dysfunction has been suggested as one of the pathophysiological risk factors for PD, the exact molecular link between the circadian clock and PD remains largely unclear. We have recently demonstrated that $REV-ERB{\alpha}$, a circadian nuclear receptor, serves as a key molecular link between the circadian and DAergic systems. It competitively cooperates with NURR1, another nuclear receptor required for the optimal development and function of DA neurons, to control DAergic gene transcription. Considering our previous findings, we hypothesize that $REV-ERB{\alpha}$ may have a role in the onset and/or progression of PD. In the present study, we therefore aimed to elucidate whether genetic abrogation of $REV-ERB{\alpha}$ affects PD-related phenotypes in a mouse model of PD produced by a unilateral injection of 6-hydroxydopamine (6-OHDA) into the dorsal striatum. $REV-ERB{\alpha}$ deficiency significantly exacerbated 6-OHDA-induced motor deficits as well as DAergic neuronal loss in the vertebral midbrain including the SN and the ventral tegmental area. The exacerbated DAergic degeneration likely involves neuroinflammation-mediated neurotoxicity. The $REV-erb{\alpha}$ knockout mice showed prolonged microglial activation in the SN along with the over-production of interleukin $1{\beta}$, a pro-inflammatory cytokine, in response to 6-OHDA. In conclusion, the present study demonstrates for the first time that genetic abrogation of $REV-ERB{\alpha}$ can increase vulnerability of DAergic neurons to neurotoxic insults, such as 6-OHDA, thereby implying that its normal function may be beneficial for maintaining DAergic neuron populations during PD progression.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.286-294
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• 2011

Cable modems typically are implemented by a forward error correction(FEC) scheme. The ITU-T Recommendation J-38 Annex B specifies using 64- and 256- quadrature amplitude modulation (QAM) and extended RS coding scheme. In implementing the cable modem, there are some problems to fabricate and fitting on FPGA chip. First, many clocks are needed in implementing cable modem because of different code rate and different modulation types. To reduce the number of clocks, we use the two memories, which are different clock speed for reading and writing data. Second, this system lost the bit-synchronization and frame-synchronization in decoder, the system recognize that all data is error. This paper solves the problems by using simple 5-stage registers and unique sync-word. Based on solutions for about problems, the cable modem is fabricated on FPGA chip name as Vertex II pro xc2vp30-5 by Xilinx, and we confirmed the effectiveness of the results.