• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.357-360
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.2
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• pp.145-158
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• 1997

Method for synchronizing multimedia data is needed to support continuous transmission of multimedia data through a network in a bounded time and it also required for supporting continuous presentation of multimedia data with the required norminal playout rate in distributed network environments. This paper describes a new synchronization method for supporting delay-sensitive multimedia Presentation without degration of Quality of services of multimedia application. It mainly aims to support both intermedia and intermedia synchronization by absorbing network variations which may cause skew or jitter. In order to remove asynchonization problems, we make use of logical time system, dynamic buffer control method, and adjusting synchronization intervals based on the quality of services of a multimedia. It might be more suitable for working on distribute[1 multimedia systems where the network delay variation is changed from time to time and no global clock is supported. And it also can effectively reduce the amount of buffer requirements needed for transfering multimedia data between source and destination system by adjusting synchronization intervals with acceptable packet delay limits and packet loss rates.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.4
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• pp.163-176
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• 2013

Cloud-based streaming game service has numerous merits, but it may suffer from presentation latency in a thin-client. It is an important issue especially for game service which needs instantaneous response to user inputs. This research proposes the methods for reducing the presentation latency between the server unit and the thin-client unit. The approaches proposed to be employed with server unit include the source/sync video format equalization, encoding format configuration according to the media type, and the S/W implementation for transmitting clock periodically. The methods for the thin-client unit include the decreasing the number of instructions, use of light encryption algorithm, and improvement on H/W decoding. The proposed schemes are tested with a commercialized streaming service platform, which reveals the reduction of presentation latency as large as a few hundred milliseconds and reaches the acceptable level (about 100 milliseconds).

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.176-182
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• 2014

This paper introduces the development of global fringe search (GFS) software for preprocessing of Daejeon Correlator. In case of the VLBI observation, a observer conducts the observation for the reference sources with strong and point-like radio stars on schedule in order to confirm the well-observedness of the radio source by the radio telescope. The correlator performs the correlation for the reference sources to detect the fringe completely. We developed the GFS software by calculating the precise delay time between each observatory based on specific observatory. Then, this software calculates the precise delay time by using the delay model (correlator model) of reference source and information of time offset between the Hydrogen Maser frequency standard and GPS (Global Positioning System) clock located in each observatory through the correlation preprocessing. In order to confirm the performance of the developed software, experiments were carried out for the reference sources and target sources observed by the KaVA (KVN and VERA Array). Experimental results show that the GFS software has effectively good performance by finding the precise delay time offset according to the comparison between the compensated delay time offset and one without compensation.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Korean Journal of Agricultural and Forest Meteorology
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• v.19 no.3
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• pp.164-173
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• 2017

Alternative cropping systems would be one of climate change adaptation options. Suitable areas for a crop could be identified using a climate suitability model. The EcoCrop model has been used to assess climate suitability of crops using monthly climate surfaces, e.g., the digital climate map at high spatial resolution. Still, a high-performance computing approach would be needed for assessment of climate suitability to take into account a complex terrain in Korea, which requires considerably large climate data sets. The objectives of this study were to implement a script for R, which is an open source statistics analysis platform, in order to use the EcoCrop model under a parallel computing environment and to assess climate suitability of maize using digital climate maps at high spatial resolution, e.g., 1 km. The total running time reduced as the number of CPU (Central Processing Unit) core increased although the speedup with increasing number of CPU cores was not linear. For example, the wall clock time for assessing climate suitability index at 1 km spatial resolution reduced by 90% with 16 CPU cores. However, it took about 1.5 time to compute climate suitability index compared with a theoretical time for the given number of CPU. Implementation of climate suitability assessment system based on the MPI (Message Passing Interface) would allow support for the digital climate map at ultra-high spatial resolution, e.g., 30m, which would help site-specific design of cropping system for climate change adaptation.

• 한국해양학회지
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• v.30 no.5
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• pp.467-479
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• 1995

To investigate the current structures and diffusion characteristics in Youngil Bay, a systematic field observations of current velocity, drogue tracking, dye diffusion experiment and aerial photographing were performed. The flow patterns in the surface layer of the bay depend more strongly on the wind and ocean current than the tidal current, and the patterns in the middle are predominated by the ocean current. The residual currents in the surface generally flow toward the inner bay through the western and central areas of the bay, and then the currents go toward the ocean along the eastern shore of the bay with anti-clock-wise circulation. The residual currents in the surface of the eastern cease are not nearly influenced by the wind, and the currents always move northward to northeastward. However, the currents in the western shore depend strongly on the wind and the outflow of the Huntsman River, that is, the residual currents go northward to northeastward when the southerly to westerly winds blow or a large amount of flow from the river discharge. The residual currents in the middle layer flow toward the inner bay along the western shore of the bay, and the incomed currents go out to the ocean along the eastern shore with anticlockwise circulation. The diffusion of dye patch by the instantaneous point source shows a similar pattern to the drogue trajectory, and the apparent diffusion coefficients of the dye patch by Fick's theory is 1.14${\times}$10$^4$ cm$^2$/s. The behavior of the river discharges in flood shows a band type's effluent pattern toward the outer bay along the western coast.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.304-315
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• 2001

In this paper, we peformed the real-time implementation of AMR(Adaptive Multi-Rate) speech coding algorithm which is adopted for IMT-2000 service using TMS320C6201, i.e., a Texas Instrument´s fixed-point DSP. With the ANSI C source code released from ETSI, optimization is performed to make it run in real-time with memory as small as possible using the C compiler and assembly language. Implemented AMR speech codec has the size of 32.06 kWords program memory, 9.75 kWords data RAM memory, and 19.89 kWords data ROM memory. And, The time required for processing one frame of 20 ms length speech data is about 4.38 ms, and it is short enough for real-time operation. It is verified that the decoded result of the implemented speech codec on the DSP is identical with the PC simulation result using ANSI C code for test sequences. Also, actual sound input/output test using microphone and speaker demonstrates its proper real-time operation without distortions or delays.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.