• Journal of the Korea Society of Computer and Information
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• v.25 no.7
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• pp.1-8
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• 2020

In this paper, we present an implementation of high speed image data transfer using XDMA for a video signal generation / acquisition device developed as a military test equipment. The technology proposed in this study obtains efficiency by replacing the method of copying data using the system buffer in the kernel area with the transmission and reception through the DMA engine in the FPGA. For this study, the device was developed as a PXIe platform in consideration of life cycle, and performance was maximized by using a low-cost FPGA considering mass productivity. The video I/O board implemented in this paper was tested by changing the AXI interface clock frequency and link speed through the existing memory copy method. In addition, the board was constructed using the DMA engine of the FPGA, and as a result, it was confirmed that the transfer speed was increased from 5~8Hz to 140Hz. The proposed method will contribute to strengthening defense capability by reducing the cost of device development using the PXIe platform and increasing the technology level.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.140-148
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• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.48-55
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• 2009

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.7-13
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• 2010

In this paper, we proposed a processor architecture that is suitable for next generation embedded applications, especially for personal information devices such as smart phones, tablet PC. Latest high performance embedded processors are developed to achieve high clock speed. Because increasing performance makes design more difficult and induces large overhead, architectural evolution in embedded processor field is necessary. Among more enhanced processor types, out-of-order superscalar cannot be a candidate for embedded applications due to its excessive complexity and relatively low performance gain compared to its overhead. Therefore, new architecture with moderate complexity must be designed. In this paper, we developed a low-cost SMT architecture model and compared its performance to other architectures including scalar, superscalar and multiprocessor. Because current personal information devices have a tendency to execute multiple tasks simultaneously, SMT or CMP can be a good choice. And our simulation result shows that the efficiency of SMT is the best among the architectures considered.

• Journal of Korea Multimedia Society
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• v.16 no.4
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• pp.483-492
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• 2013

SURF is an algorithm which extracts feature points and generates their descriptors from input images, and it is being used for many applications such as object recognition, tracking, and constructing panorama pictures. Although SURF is known to be robust to changes of scale, rotation, and view points, it is hard to implement it in real time due to its complex and repetitive computations. Using 3.3 GHz Pentium, in our experiment, it takes 240ms to extract feature points and create descriptors in a VGA image containing about 1,000 feature points, which means that software implementation cannot meet the real time requirement, especially in embedded systems. In this paper, we present a hardware architecture that can compute the SURF algorithm very fast while consuming minimum hardware resources. Two key concepts of our architecture are parallelism (for repetitive computations) and efficient line memory usage (obtained by analyzing memory access patterns). As a result of FPGA synthesis using Xilinx Virtex5LX330, it occupies 101,348 LUTs and 1,367 KB on-chip memory, giving performance of 30 frames per second at 100 MHz clock.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10A
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• pp.1015-1022
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• 2007

In this paper, dual-band digital codec for UHF(Ultra High Frequency) and MW(Micro Wave) is proposed for an RFID reader system. Most RFID systems have been supported only one protocol. But, There are many protocols of each bandwidth. Especially, UHF bandwidth which is widely used on the globe consists of A,B,C type, and more standards will be established. Recently, Since an interest about mobile RFID system is increasing, the RFID system with more than one protocol will be need. Therefore, this paper suggests a dual-band digital codec with UHF and MW bands for an RFID reader system. Standards used in this system are 18000-6C and 18000-4 standards. The digital codec is synthesize by the Quartus II compiler. Target device is EPC20Q240C8 which is family of CycloneII. Main Clock is 19.2MHz and elements of FPGA which is used for the system is 18,752.

• Journal of the Society of Disaster Information
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• v.10 no.3
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• pp.374-387
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• 2014

Since the sexual violence crime has a high probability of repeated crime, the electronic monitoring system has been introduced as a measure to it. And this system allows the police to know the location of former criminal around the clock through the electronic device, the former criminal has the psychological/mental oppression which can restrain the intention of crime to a degree. However, there is a limit in blocking criminals with strong will from repeated crime. The next-generation intelligent electronic anklet currently under study collects and analyzes the change bio-data in real time through the location information of electronic monitoring target and attached sensor. This study is aimed to predict the symptom of crime occurrence in advance based on this and block the crime intention in advance or stop the ongoing crime before it is expanded.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.34-41
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• 2002

This paper describes a scalable implementation method of a word-based RSA cryptoprocessor using pseudo carry look-ahead adder The basic organization of the modular multiplier consists of two layers of carry-save adders (CSA) and a reduced carry generation and Propagation scheme called the pseudo carry look-ahead adder for the high-speed final addition. The proposed modular multiplier does not need complicated shift and alignment blocks to generate the next word at each clock cycle. Therefore, the proposed architecture reduces the hardware resources and speeds up the modular computation. We implemented a single-chip 1024-bit RSA cryptoprocessor based on the word-based modular multiplier with 256 datapaths in 0.5${\mu}{\textrm}{m}$ SOG technology after verifying the proposed architectures using FPGA with PCI bus.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.3029-3034
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• 2014

The paper describes the scleral diagnostic system implementation for human eyes by using the scleral color code and vessels sign pattern code generations. The system is based on the high performance DSP image signal processor, programmable gain control for preprocessing and RISC SD frames storage. RGB image signals are optimized by PGC, the edge image is detected form the gray image converted. The processing algorithms are executed by scleral color code generation and scleral vessels sign pattern code creation for discriminating and matching. The scleral symptomatic color code is generated by YCbCr values at memory map tolerated and the vessel sign pattern code is created by digitizing the 24 clock and 13 ring zones, overlay matching and tolerances. The experimental results for performance are that the system runs 40ms, and the color and pattern for diagnostic errors are around 20% and 24% on average. The system and technique enable a scleral diagnosis with subdividing the patterns and patient database.