• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.583-586
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• 2004

In this paper, we have analyzed the performance of synchronization of CCK(Complementary Code Keying) modulation scheme used for IEEE 802.11g wireless LAM system supporting 54 Mbps of high speed data rate over 2.4 GHz. At receiver, the clock frequency offset is caused by noise or fading. This frequency error occurs the offset of clock timing and causes ISI. Therefore the tracking is required to reduce the clock timing offset. The DLL(Delay Lock Loop), asychronization mode, performing tacking the clock is used for the simulation. The simulation result shows jitter variance and BER performance in the AWGN and multipath fading channel environment.

• Journal of the Korea Society of Computer and Information
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• v.18 no.7
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• pp.47-55
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• 2013

Most of the applications implemented in embedded systems use timers equipped in MCU. The purposes of timer usage of the applications lie in a wide range of areas such as implementing software timers of real-time operating systems to measuring processing time of sensors. The elapsed times measured by the applications are various in length as well as in precision ranging from several us to several hundreds of ms. The paper analyzes the timing error factors caused by un- synchronizing timer clock pulse when timers are manipulated, and proposes a method of how to synchronize timer clock pulse to reduce the timing errors. As a result of an experiment, this paper shows that an error of 230us is reduced within 10us in case of appling the proposed method to a 4096Hz timer prescaled from 32768Hz by 8.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.7
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• pp.669-676
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• 2015

In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1765-1773
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• 1997

The communication systems which include PLL may have cycle clip problem because of channel noise. The cycle slip problem occurs the synchronization loss of communication system and it may be fatal to the synchronous stream cipher system. While continuous resynchronization is used to lessen the risk of synchronization it has some problems. In this paper, we propose the method which solve the problems by using continuous resynchronization with the clock recovery technique. If the counted value of real clock pulse in reference duration is not same as that of normal state, we decide the cycle slip has occurred. The damaged clock by cycle slip is compensated by adding or subtracting the clock pulse according to the type of cycle slip. It reduced the time for resynchronization by twenty times. It means that 17.8% of data for transmit is compressed.

• Journal of Positioning, Navigation, and Timing
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• v.13 no.1
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• pp.111-115
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• 2024

This study builds a machine learning model optimized for clocks among various techniques in the field of artificial intelligence and applies it to clock stabilization or synchronization technology based on atomic clock noise characteristics. In addition, the possibility of providing stable source clock data is confirmed through the characteristics of machine learning predicted values during holdover of atomic clocks. The proposed machine learning model is evaluated by comparing its performance with the AutoRegressive Integrated Moving Average (ARIMA) model, an existing statistical clock prediction model. From the results of the analysis, the prediction model proposed in this study (MSE: 9.47476) has a lower MSE value than the ARIMA model (MSE: 221.2622), which means that it provides more accurate predictions. The prediction accuracy is based on understanding the complex nature of data that changes over time and how well the model reflects this. The application of a machine learning prediction model can be seen as a way to overcome the limitations of the statistical-based ARIMA model in time series prediction and achieve improved prediction performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1004-1009
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• 2004

Precise time synchronization is a main technology in high-speed communications, parallel and distributed processing systems, Internet information industry and electronic commerce. Synchronized clocks are useful for many leasers. Often a distributed system is designed to realize some synchronized behavior, especially in real-time processing in factories, aircraft, space vehicles, and military applications. Nowadays, time synchronization has been compulsory thing as distributed processing and network operations are generalized. A network time server obtains, keeps accurate and precise time by synchronizing its local clock to standard reference time source and distributes time information through standard time synchronization protocol. This paper describes design issues and implementation of a network time server for time synchronization especially based on a clock model. The system uses GPS (Global Positioning System) as a standard reference time source and offers UTC (universal Time coordinated) through NTP (Network Time protocol). Implementation result and performance analysis are also presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.446-455
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• 2001

In this paper, the precise synchronized clock generator using GPS receiver is presented. The GPS receiver provides a synchronized IPPS signal which guaranties a reliable standard time mark. This signal allows us to do time synchronization and correct the time step. We designed and implemented the precise synchronized clock generator based on DPLL in order to generate a high-resolution clock from a low-cost inaccurate oscillator with ALTERA FLEX EPM6016TC144-3. We also implemented a hardware unit and proved that the unit provides 1MHz clock output which had a high resolution and accuracy when it was combined with GPS receiver.

• Journal of Broadcast Engineering
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• v.23 no.2
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• pp.197-205
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• 2018

Panoramic image is one of the technologies that are commonly used today. However, technical difficulties still exist in panoramic video production. Without a special camera such as a 360-degree camera, making panoramic video becomes more difficult. In order to make a panoramic video, it is necessary to synchronize the timeline of multiple videos shot at multiple locations. However, the timeline synchronization method using the internal clock of the camera may cause an error due to the difference of the internal hardware. In order to solve this problem, timeline synchronization between multiple videos using visual information or auditory information has been studied. However, there is a problem in accuracy and processing time when using video information, and there is a problem in that, when using audio information, there is no synchronization when there is sensitivity to noise or there is no melody. Therefore, in this paper, we propose a timeline synchronization method between multiple video using audio waveform. It shows higher synchronization accuracy and temporal efficiency than the video information based time synchronization method.

• The KIPS Transactions:PartC
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• v.19C no.3
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• pp.209-214
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• 2012

Time synchronization is important role in a network, especially in Wireless Sensor Network (WSN) which is required for time-critical applications such as surveillance, tracking, data fusion and scheduling. Time synchronization in WSN should meet the other different requirements than the one in other networks because WSN has critical resource constraints, especially power consumption. This paper presents a new time synchronization scheme for WSN, which is energy efficient by reducing communication overhead. Simulation test shows this new scheme has better energy efficiency and performance of accuracy than existing schemes proposed previously.