• Journal of Positioning, Navigation, and Timing
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• v.4 no.2
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• pp.43-55
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• 2015

In the case of satellite navigation positioning, the shielding of satellite signals is determined by the environment of the region at which a user is located, and the navigation performance is determined accordingly. The accuracy of user position determination varies depending on the dilution of precision (DOP) which is a measuring index for the geometric characteristics of visible satellites; and if the minimum visible satellites are not secured, position determination is impossible. Currently, the GLObal NAvigation Satellite system (GLONASS) of Russia is used to supplement the navigation performance of the Global Positioning System (GPS) in regions where GPS cannot be used. In addition, the European Satellite Navigation System (Galileo) of the European Union, the Chinese Satellite Navigation System (BeiDou) of China, the Quasi-Zenith Satellite System (QZSS) of Japan, and the Indian Regional Navigation Satellite System (IRNSS) of India are aimed to achieve the full operational capability (FOC) operation of the navigation system. Thus, the number of satellites available for navigation would rapidly increase, particularly in the Asian region; and when integrated navigation is performed, the improvement of navigation performance is expected to be much larger than that in other regions. To secure a stable and prompt position solution, GPS-GLONASS integrated navigation is generally performed at present. However, as available satellite navigation systems have been diversified, finding the minimum satellite constellation combination to obtain the best navigation performance has recently become an issue. For this purpose, it is necessary to examine and predict the navigation performance that could be obtained by the addition of the third satellite navigation system in addition to GPS-GLONASS. In this study, the current status of the integrated navigation performance for various satellite constellation combinations was analyzed based on 2014, and the navigation performance in 2020 was predicted based on the FOC plan of the satellite navigation system for each country. For this prediction, the orbital elements and nominal almanac data of satellite navigation systems that can be observed in the Korean Peninsula were organized, and the minimum elevation angle expecting signal shielding was established based on Matlab and the performance was predicted in terms of DOP. In the case of integrated navigation, a time offset determination algorithm needs to be considered in order to estimate the clock error between navigation systems, and it was analyzed using two kinds of methods: a satellite navigation message based estimation method and a receiver based method where a user directly performs estimation. This simulation is expected to be used as an index for the establishment of the minimum satellite constellation for obtaining the best navigation performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.2000-2011
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• 2001

In this Paper, we convert conventional low speed(1x, 6x) DVD systems designed by analog PLL(Phase Locked Loop) into digital PLL to operate at high speed systems flexibly, and present optimal DPLL model in high speed(20x) DVD systems. Especially, we focused on the design of DPLL that can overcome channel effects such as bulk delay, sampling clock frequency offset and asymmetry phenomenon in high speed DVD systems. First, the modified Early-Late timing error detector as digital timing recovery scheme is proposed. And the four-sampled compensation algorithm using zero crossing point as asymmetry compensator is designed to achieve high speed operation and strong reliability. We show that the proposed timing recovery algorithm provides enhanced performances in jitter valiance and SNR margin by 4 times and 3dB respectively. Also, the new four-sampled zero crossing asymmetry compensation algorithm provides 34% improvement of jitter performance, 50% reduction of compensation time and 2.0dB gain of SNR compared with other algorithms. Finally, the proposed systems combined with asymmetry compensator and DPLL are shown to provide improved performance of about 0.4dB, 2dB over the existing schemes by BER evaluation.

• Korean Journal of Agricultural and Forest Meteorology
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• v.11 no.2
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• pp.61-71
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• 2009

Most deciduous trees in temperate zone are dormant during the winter to overcome cold and dry environment. Dormancy of deciduous fruit trees is usually separated into a period of rest by physiological conditions and a period of quiescence by unfavorable environmental conditions. Inconsistent and fewer budburst in pear orchards has been reported recently in South Korea and Japan and the insufficient chilling due to warmer winters is suspected to play a role. An accurate prediction of the flowering time under the climate change scenarios may be critical to the planning of adaptation strategy for the pear industry in the future. However, existing methods for the prediction of budburst depend on the spring temperature, neglecting potential effects of warmer winters on the rest release and subsequent budburst. We adapted a dormancy clock model which uses daily temperature data to calculate the thermal time for simulating winter phenology of deciduous trees and tested the feasibility of this model in predicting budburst and flowering of Niitaka pear, one of the favorite cultivars in Korea. In order to derive the model parameter values suitable for Niitaka, the mean time for the rest release was estimated by observing budburst of field collected twigs in a controlled environment. The thermal time (in chill-days) was calculated and accumulated by a predefined temperature range from fall harvest until the chilling requirement (maximum accumulated chill-days in a negative number) is met. The chilling requirement is then offset by anti-chill days (in positive numbers) until the accumulated chill-days become null, which is assumed to be the budburst date. Calculations were repeated with arbitrary threshold temperatures from $4^{\circ}C$ to $10^{\circ}C$ (at an interval of 0.1), and a set of threshold temperature and chilling requirement was selected when the estimated budburst date coincides with the field observation. A heating requirement (in accumulation of anti-chill days since budburst) for flowering was also determined from an experiment based on historical observations. The dormancy clock model optimized with the selected parameter values was used to predict flowering of Niitaka pear grown in Suwon for the recent 9 years. The predicted dates for full bloom were within the range of the observed dates with 1.9 days of root mean square error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.