• 한국가정과학회지
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• 제1권2호
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• pp.61-74
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• 1998

The purpose of this study is to investigate residents subjective opinion of the noise on the low-rise multifamily house in U.S.A. The results of this study can be applied for the prevention of noise when planning cities, roads, and multifamily houses in Korea. The subjects of this study are three kinds of multifamily houses and their 109 residents in Athens, U.S.A. The results of this study are as follows. The residents felt the noise from lawn mowers and the sound from filter fans of air conditioners were higher than in the other external noise. The residents daily activities were disturbed a little by the external noise. Of the internal noise, the air home sound was recognized a little by residents. They only felt a moderate sound level from the building services of the solid borne sound. They suffered worse from noise in the summer and they felt worse from 16∼20 o'clock due to noise. The residents who were living in town houses felt better than those in the other multifamily houses. (Korean J Human Ecology 1(2):61∼74. 1998)

• 한국통신학회논문지
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• 제18권12호
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• pp.1983-1993
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• 1993

본 논문에서는 full-flash A/D 변환기에서 전력소모를 줄이는 방법과 그의 회로를 제안하였다. Full-flash A/D 변환기에서 해상도가 증가하면 전압비교기의 수는 지수함수적으로 증가하며 모든 전압비교기가 항상 동작하여 전력 소모가 많으므로 제안하는 구조에서는 입력 신호의 크기에 까라 그 영역에 해당하는 위치에 있는 전압비교기를 선택적으로 켜줌으로써 전력 소모를 줄인다. 입력 신호의 크기를 판별하기 위하여 입력 신호의 범위를 찾는 회로를 설계하였다. 클리치 잡음을 줄일 수 있는 클럭 발생회로를 설계하여 사용함으로써 전압 비교기의 전류원에서 발생하는 잡음을 일반적인 클럭을 사용했을 때와 비교하여 1/4로 줄였다. 설계한 A/D 변환기는 out-off 주파수가 5GHz 인 1.2 m의 BiCMOS 공정으로 제작하였다. 이는 350Msamples /s의 변환 속도를 가지며 소모 전력은 900mW이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• 한국통신학회논문지
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• 제19권11호
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• pp.2160-2169
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• 1994

동기식통신망의 클럭들에서 발생되는 위상시간에러(phase time error)의 성분은 주로 플리커잡음(flicker noise)및 랜덤워크잡음(random-walk noise)이다. 본 논문에서는 먼저 주파수 안정도에 대한 측정표준을 설명하였다. 그리고 백색잡음으로부터 플리커잡음 및 랜덤워크잡음을 디지털 컴퓨터상에서 생성시킬 수 있는 알고리즘을 소개하였는데, 특히 플리커잡음에 대해서는 단수(stage number) N, 시정수비(time constant ratio) K와 플리커잡음생성대역폭의 관계를 예를 들어 규명하였다. 동기식망에서 발생되는 위상시간에러를 실제 측정한 결과에 따라서 이 알고리즘을 이용하여 컴퓨터로 클럭의 위상시간에러를 시뮬레이션하였다.

• 한국군사과학기술학회지
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• 제19권3호
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• pp.379-386
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• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

• 한국통신학회논문지
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• 제27권9C호
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• pp.879-885
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• 2002

통신 시스템의 성능은 여러 가지 요구 조건을 고려하여 측정되어져야 한다. 이러한 목적으로 잡음 발생기는 주어진 특성을 갖는 잡음 신호를 생성하는데 사용되는 시스템이다. 본 논문에서는 최근에 제안된 DCT를 이용한 잡음 발생기에서 DCT를 제외한 회로의 면적을 약 44∼47% 정도 줄이는 구조를 제안한다. 또한, 제안된 구조는 내부의 빠른 클럭을 사용하지 않게 되어 74∼77% 정도의 전력소모를 감소시켰다.

• ETRI Journal
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• 제42권4호
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• pp.480-490
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• 2020

More than 42 000 fires occur nationwide and cause over 2500 casualties every year. There is a lack of specialized equipment, and rescue operations are conducted with a minimal number of apparatuses. Through-the-wall radars (TTWRs) can improve the rescue efficiency, particularly under limited visibility due to smoke, walls, and collapsed debris. To overcome detection challenges and maintain a small-form factor, a TTWR system-on-chip (SoC) and its architecture have been proposed. Additive reception based on coherent clocks and reconfigurability can fulfill the TTWR demands. A clock-based single-chip infrared radar transceiver with embedded control logic is implemented using a 130-nm complementary metal oxide semiconductor. Clock signals drive the radar operation. Signal-to-noise ratio enhancements are achieved using the repetitive coherent clock schemes. The hand-held prototype radar that uses the TTWR SoC operates in real time, allowing seamless data capture, processing, and display of the target information. The prototype is tested under various pseudo-disaster conditions. The test standards and methods, developed along with the system, are also presented.

• 한국통신학회논문지
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• 제27권10C호
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• pp.980-986
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• 2002

하나의 클럭원으로 동기 되는 고속의 데이터 통신 시스템에서, 데이터와 클럭 사이의 다른 라우팅 경로나, 부품들의 다른 전달지연시간 또는 외부 잡음에 의한 데이터나 클럭의 불안정한 위상과 같은 여러 이유들로 인해 데이터를 잃어버릴 수가 있다. 본 논문에서는 이렇게 잃어버린 데이터를 탐지하고 원래의 데이터로 복원하여 보상 출력하는 기능을 갖는 디지털 회로를 제안하고 구현을 기술한다. 특히, 이러한 보상회로는 광 분야등과 같이 고속의 데이터 전송을 위한 통신 시스템에서 강한 안정성을 가지며 BER개선에 상당히 크게 영향을 준다. 이 회로는 Verilog HDL로 구현이 되었으며 통신 및 데이터 전송관련 디지털 ASIC구현에 기본적으로 응용이 가능하다.

• 전기학회논문지P
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• 제60권4호
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• pp.227-235
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• 2011

This paper describes a PMSM control algorithm for realizing a low-cost motor drive system using a general purpose microcontroller. The proposed sensorless algorithm consists of the current observer and the sensorless scheme based on instantaneous reactive power. Also the control board system is not the high-cost DSP(digital signal processor) system but the general purpose microcontroller and it allows to reduce the unit cost of the motor system. However the clock frequency of the proposed microcontroller is one-fifths for the clock frequency of the DSP. In addition, the switching frequency must be selected as the lower frequency because of complex mathematic modeling of the sensorless algorithm. the low switching frequency augments the noise of the motor and might make accurate speed control impossible. Thus this paper proposes the optimization method to supplement the drawback of the general purpose microcontroller and the usefulness of the proposed method is verified through the experiment.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.445-446
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• 2008

With the semiconductor industry evolving into the deep sub-micron (DSM) era, the crosstalk effects on interconnect lines of a chip have increasingly caused a major bottleneck for design closure. In this paper, we propose an effective design guide line to reduce cell area overhead without crosstalk noise violations by using crosstalk prevention flow with clock shielding.