• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.66-72
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• 2014

Histogram of oriented gradient (HOG) feature is widely used in vision-based pedestrian detection. The interpolation is the most important technique in HOG feature calculation to provide high detection rate. In interpolation technique of HOG feature calculation, two nearest orientation bins to gradient orientation for each pixel and the corresponding weights are required. In this paper, therefore, an efficient gradient orientation bin and weight calculation circuit for HOG feature is proposed. In the proposed circuit, pre-calculated values are defined in tables to avoid the operations of tangent function and division, and the size of tables is minimized by utilizing the characteristics of tangent function and weights for each gradient orientation. Pipeline architecture is adopted to the proposed circuit to accelerate the processing speed, and orientation bins and the corresponding weights for each pixel are calculated in two clock cycles by applying efficient coarse and fine search schemes. Since the proposed circuit calculates gradient orientation for each pixel with the interval of $1^{\circ}$ and determines both orientation bins and weights required in interpolation technique, it can be utilized in HOG feature calculation to support interpolation technique to provide high detection rate.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.3
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• pp.328-333
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• 2012

Current differential GPS (DGPS) system consists of reference station (RS), integrity monitor (IM), and control station (CS). The RS computes the pseudorange corrections (PRC) and generates the RTCM messages for broadcasting. The IM receives the corrections from the RS broadcasting and verifies that the information is within tolerance. The CS performs realtime system status monitoring and control of the functional and performance parameters. The primary function of a DGPS integrity monitor is to verify the correction information and transmit feedback messages to the reference station. However, the current algorithms for integrity monitoring have the limitations of integrity monitor functions for satellite outage or anomalies. Therefore, this paper focuses on the detection and identification methods of satellite anomalies for maritime DGPS RSIM. Based on the function analysis of current DGPS RSIM, it first addresses the limitation of integrity monitoring functions for DGPS RSIM, and then proposes the detection and identification method of satellite anomalies. In addition, it simulates an actual GPS clock anomaly case using a GPS simulator to analyze the limitations of the integrity monitoring function. It presents the brief test results using the proposed methods for detection and identification of satellite anomalies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11A
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• pp.882-890
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• 2009

In this paper, we describe a compensation method that can be used for the situation where Loran receivers lose their phase lock to the received Loran signals when Loran signals are employed for the synchronization of national infrastructures such as telecommunication networks, electric power distribution and so on. In losing the phase lock to the received signals in a Loran receiver, the inner oscillator of the receiver starts free-running and the performance of the timing synchronization signals which are locked to the oscillator's phase is very severly degraded, so the timing accuracy under 1 us for a Primary Reference Clock (PRC) required in the International Telecommunications Union (ITU) G.811 standard can not be satisfied in the situation. Therefore, in this paper, we propose a method which can compensate the phase jump by using a compensation algorithm when a Loran receiver loses its phase lock and the performance evaluation of the proposed algorithm is achieved by the Maximum Time Interval Error (MTIE) of the measured data. From the performance evaluation results, it is observed that the requirement under 1 us for a PRC can be easily achieved by using the proposed algorithm showing about 0.6 us with under 30 minutes mean interval of smoothing with 1 hour period when the loss of phase lock occurs.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.235-240
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• 2006

The paper will give an overview of the mission of GalTeC and then concentrate on two main aspects. The first more detailed aspect, is the analysis of the key performance parameters for the Galileo system services and presenting a technical overview of methods and algorithms used. The second more detailed aspect, is the service volume prediction including service dimensioning using the Prediction tool. In order to monitor and validate the Galileo SIS performance for Open Service (OS) and Safety Of Life services (SOL) regarding the key performance parameters, different analyses in the SIS domain and User domain are considered. In the SIS domain, the validation of Signal-in-Space Accuracy SISA and Signal-in-Space Monitoring Accuracy SISMA is performed. For this purpose first of all an independent OD&TS and Integrity determination and processing software is developed to generate the key reference performance parameters named as SISRE (Signal In Space Reference Errors) and related over-bounding statistical information SISRA (Signal In Space Reference Accuracy) based on raw measurements from independent sites (e.g. IGS), Galileo Ground Sensor Stations (GSS) or an own regional monitoring network. Secondly, the differences of orbits and satellite clock corrections between Galileo broadcast ephemeris and the precise reference ephemeris generated by GalTeC will also be compared to check the SIS accuracy. Thirdly, in the user domain, SIS based navigation solution PVT on reference sites using Galileo broadcast ephemeris and the precise ephemeris generated by GalTeC are also used to check key performance parameters. In order to demonstrate the GalTeC performance and the methods mentioned above, the paper presents an initial test result using GPS raw data and GPS broadcast ephemeris. In the tests, some Galileo typical performance parameters are used for GPS system. For example, the maximum URA for one day for one GPS satellite from GPS broadcast ephemeris is used as substitution of SISA to check GPS ephemeris accuracy. Using GalTeC OD&TS and GPS raw data from IGS reference sites, a 10 cm-level of precise orbit determination can be reached. Based on these precise GPS orbits from GalTeC, monitoring and validation of GPS performance can be achieved with a high confidence level. It can be concluded that one of the GalTeC missions is to provide the capability to assess Galileo and general GNSS performance and prediction methods based on a regional and global monitoring networks. Some capability, of which first results are shown in the paper, will be demonstrated further during the planned Galileo IOV phase, the Full Galileo constellation phase and for the different services particularly the Open Services and the Safety Of Life services based on the Galileo Integrity concept.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.444-447
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• 2011

In this paper, parallel IT(inverse transform) architecture and IQ(inverse quantization) architecture with common operation unit for the H.264/AVC decoder are proposed. By using common operation unit, the area cost and computational complexity of IQ are reduced. In order to take four execution cycles to perform IT, the proposed IT architecture has parallel architecture with one horizontal DCT unit and four vertical DCT units. Furthermore, the execution cycles of the proposed architecture is reduced to five cycles by applying two state pipeline architecture. The proposed architecture is implemented to a single chip by using Magnachip 0.18um CMOS technology. The gate count of the proposed architecture is 14.3k at clock frequency of 13MHz and the area of proposed IQ is reduced 39.6% compared with the previous one. The experimental result shows that execution cycle the proposed architecture is about 49.09% higher than that of the previous one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.431-435
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• 2011

This paper presents optimized searching technique to improve the performance of H.264/AVC. The proposed CAVLC encoder uses forward and backward searching algorithm to compute the parameters. By zero-block skipping technique and pipelined scheduling, the proposed CAVLC encoder can obtain better performance. The experimental result shows that the proposed architecture needs only 66.6 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 13.8% than that of previous designs. The proposed CAVLC encoder was implemented using VerilogHDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 15.6K with 125Mhz clock frequency.

• Journal of Navigation and Port Research
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• v.37 no.4
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• pp.375-381
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• 2013

In order to establish eLoran system it needs the betterment of a receiver and a transmitter, the add of data channel to loran pulse for loran system information and the differential Loran for compensating Loran-c signal. Precise ASF database map is essential if the Loran delivers the high absolute accuracy of navigation demanded at maritime harbor entrance. In this study we developed the ASF mapping method using predicted ASFs compensated by the measured ASFs for maritime in the harbor. Actual ASF is measured by the legacy Loran signal transmitted from Pohang station in the GRI 9930 chain. We measured absolute propagation delay between the Pohang transmitting station and the measurement points by comparing with the cesium clock for the calculation of the ASFs. Monteath model was used for the irregular terrain along the propagation path in the Yeongil Bay. We measured the actual ASFs at the 12 measurement points over the Yeongil Bay. In our ASF-mapping method we estimated that the each offsets between the predicted and the measured ASFs at the 12 spaced points in the Yeongil. We obtained the ASF map by adjusting the predicted ASF results to fit the measured ASFs over Yeungil bay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.83-90
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• 2007

In this paper, we propose an implementation and an algorithm of 'Jitter and Glitch Removing Circuit' for UHF RFID reader system based on ISO/IEC 18000-6C standard. We analyze the response of TI(Texas Instrument) Gen2 tag with a reader using the proposed algorithm. In ISO/IEC 18000-6C standard, a bit rate accuracy(tolerance) is up to +/-22% during tag-to-interrogator communication and +/-1% during interrogator-to-tag communication. In order to solve tolerance problems, we implement the Jitter and Glitch Removing Circuit using the concept of tolerance and tolerance-accumulation instead of PLL(DPLL, ADPLL). The main clock is 19.2MHz and the LF(Link Frequency) is determined as 40kHz to meet the local radio regulation in korea. As a result of simulations, the error-rate is zero within 15% tolerance of tag responses. And in the case of using the adaptive LF generation circuit, the error-rate varies from 0.000589 to zero between 15% and 22% tolerance of tag responses. In conclusion, the error-rate is zero between 0%-22% tolerance of tag response specified in ISO/IEC 18000-6C standard.