• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.42 no.2 s.302
• /
• pp.27-36
• /
• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.1
• /
• pp.28-37
• /
• 2010

In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.1
• /
• pp.15-22
• /
• 2008

In this paper, we propose a numerical analysis on reversed current of distributed amplifier based on transmission line theory and proposed a theory to obtain optimum transmission line length to minimize the reversed currents by cancelling those components. The reversed current is analyzed as being simply absorbed into the terminal resistance in the conventional analysis. In the proposed analysis, however, they are designed to be cancelled by each other with opposite phase by the optimal length of the transmission lint Circuit simulation and implementation using pHEMT transistor were performed to validate the proposed theory with the cutoff frequency of 3.6 GHz. From the measurement, maximum gain of 14.5dB and minimum gain of 12.3dB were achieved In the operation band. Moreover, measured efficiency of the proposed distributed amplifier is 25.6% at 3 GHz, which is 7.6%, higher than the conventional distributed amplifier. Measured output power Is about 10.9dBm, achieving 1.7dB higher output power than the conventional one. Those improvement is thought to be based on the cancellation of refersed current.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.8
• /
• pp.866-872
• /
• 2007

In this paper, we present a frequency tunable and compact antenna which consists of a first-order Peano curve, two shorting posts, and two inductors which are serially connected between the posts and the edge of the Peano curve. By properly choosing the inductance of two inductors, the operating frequency of the antenna can be controlled without sacrificing the fractional bandwidth. To give good demonstration of the operating mechanism, the equivalent circuit of this antenna is included. To validate the simulation results, we have fabricated the several antennas of being integrated with different inductors, and the measured results show a good agreement with the simulated ones. The measured results reveal that the operating frequency is shifted from 1.47 GHz to 0.586 GHz without the decrease of the input impedance bandwidth. In case of integrating two inductors of 91nH and 470nH, the electric size of the antenna is only $0.0246 {\lambda}{\times}0.0246{\lambda}{\times}0.0114{\lambda}$. The measured fractional bandwidth$(S_{11}{\leq}-10 dB)$ and the radiation efficiency of the antenna are 5.22% and 47.25%, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.11
• /
• pp.1172-1182
• /
• 2014

In these days, many kinds of goods are more light and more integrated. As frequency range of mobile applications have increased to improve performance of antenna furthermore, EMI(ElectroMagnetic Interference) problem has frequently caused by disturbance of antenna in device which aggravates other circuit. This paper proposes a technique for the prediction of noise power to the transmission line from antenna located near the line. Although noise power transferred to transmission line is varied by source impedance of antenna and load impedance of transmission line basically, the power magnitude can be presented in a square form of S-parameter between antenna and transmission line due to small variation of transferred power. For this reason, we can use the index expressed the transferred power varied along geometrical shapes of transmission line. As a result, big difference is occurred along location of antenna especially the bended line. And this such experiment is correspond with simulation, these results have meaning physically considering electromagnetic field distribution in near and far field. HFSS of Ansys and CPW with ground is used in this paper.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.9
• /
• pp.1037-1044
• /
• 2010

In this paper, a new size-reduced, wideband ring-hybrid coupler is presented, and a design of a planar single-balanced doubler using the ring-hybrid is shown. This ring-hybrid coupler employs a pair of ultra-wideband transitions for phase inversion, which consists of in-phase and out of-phase transitions providing a good amplitude and phase balances for wide frequency ranges. The implemented ring-hybrid is 65 % smaller than conventional ring-hybrids, and provides 92.5 % and 81.3 % bandwidth at $\sum$ and $\Delta$ ports, respectively. Thanks to good amplitude and phase balances over wide bandwidth, the ring-hybrid can be applied to implement various balanced components. The implemented single-balanced doubler utilizing the ring-hybrid exhibits typical conversion loss of 10.5 dB for the output frequency range of 4~12 GHz with fundamental suppression level of 30 dB. The performance was also well-predicted with the nonlinear circuit simulation.

• Journal of the Korean Society of Safety
• /
• v.32 no.2
• /
• pp.34-37
• /
• 2017

In recent emerging industry, Display field becomes bigger and bigger, and also semiconductor technology becomes high density integration. In Flat Panel Display, there is an issue that electrostatic phenomenon results in fine dust adsorption as electrostatic capacity increases due to bigger size. Destruction of high integrated circuit and pattern deterioration occur in semiconductor and this causes the problem of weakening of thermal resistance. In order to solve this sort of electrostatic failure in this process, Soft X-ray ionizer is mainly used. Soft X-ray Ionizer does not only generate electrical noise and minute particle but also is efficient to remove electrostatic as it has a wide range of ionization. X-ray Generating efficiency has an effect on soft X-ray Ionizer affects neutralizing performance. There exist variable factors such as type of anode, thickness, tube voltage etc., and it takes a lot of time and financial resource to find optimal performance by manufacturing with actual X-ray tube source. MCNPX (Monte Carlo N-Particle Extended) is used for simulation to solve this kind of problem, and optimum efficiency of X-ray generation is anticipated. In this study, X-ray generation efficiency was measured according to target material thickness using MCNPX under the conditions that tube voltage is 5 keV, 10 keV, 15 keV and the target Material is Tungsten(W), Gold(Au), Silver(Ag). At the result, Gold(Au) shows optimum efficiency. In Tube voltage 5 keV, optimal target thickness is $0.05{\mu}m$ and Largest energy of Light flux appears $2.22{\times}10^8$ x-ray flux. In Tube voltage 10 keV, optimal target Thickness is $0.18{\mu}m$ and Largest energy of Light flux appears $1.97{\times}10^9$ x-ray flux. In Tube voltage 15 keV, optimal target Thickness is $0.29{\mu}m$ and Largest energy of Light flux appears $4.59{\times}10^9$ x-ray flux.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.18 no.10
• /
• pp.15-23
• /
• 2017

This paper reports a SOC(State-of-Charge) estimation method using the extended Kalman filter(EKF) algorithm, which can allow real-time implementation and reduce the error of the model and be robust against noise, to accurately estimate and evaluate the charging/discharging state of the EV(Electric Vehicle) battery. The battery was modeled as the first order Thevenin model for the EKF algorithm and the parameters were derived through experiments. This paper proposes the changed method, which can have the SOC to 0% ~ 100% regardless of the aging of the battery by replacing the rated capacity specified in the battery with the maximum chargeable capacity. In addition, This paper proposes the EKF algorithm to estimate the non-linearity interval of the battery and simulation result based on Ah-counting shows that the proposed algorithm reduces the estimation error to less than 5% in all intervals of the SOC.

• The Journal of the Acoustical Society of Korea
• /
• v.20 no.5
• /
• pp.69-75
• /
• 2001

In this paper, a fast and easy impedance matching method, which could give the impedance matching component for the general 1 or 2-port network was introduced. First, the entire network structure was defined which consists of the network part to be matched and the impedance matching part composed of inductors and capacitors. Next, the transmission matrix and input and output impedances of the entire network from the terminal impedance conditions were calculated, then the exact solutions for the matching components were obtained. To verify the efficiency of this method, this method was applied to the CDMA If band withdrawal weighted SAW transversal filter, and investigated the effects of the impedance matching before and after, through the simulation and experiment. As the result, the performance of a fractional bandwidth of 1.2%, insertion loss of 29 dB, and VSWR of 80 have improved to a factional bandwidth of 1.8％, insertion loss of 9 dB, VSWR of 3 at 85.38 MHz center frequency. The result shows that this impedance matching method could be used in the SAW devices and other types of 1 or 2-port network.

• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.859-866
• /
• 2020

This paper proposes a 2-ch DC-DC converter with a wide-input voltage range from 2.9V~5.6V for wearable AMOLED displays. For positive voltage V_POS, a boost converter is designed using an over-charged voltage permissible circuit (OPC) which generates a normal output voltage even if over-input voltage is applied, and a SPWM-PWM dual mode with 3-segmented power transistors to improve efficiency at light load. For negative voltage V_NEG, a 0.5x regulated inverting charge pump is designed to increase power efficiency. The proposed DC-DC converter was designed using a 0.18-㎛ BCDMOS process. Simulation results show that the proposed DC-DC converter generates V_POS voltages of 4.6 V and V_NEG voltage of -0.6V~-2.3V for input voltage of 2.9V to 5.6V. In addition, it has power efficiency of 49%~92%, output ripple voltage has less than 20 mV for load current range of 1 mA~70 mA.