• Title/Summary/Keyword: Circuit noise

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Analysis of Power Transfer and Noise characteristics for PCB Design of DC/DC Converter (DC/DC Converter의 PCB 설계에 따른 전력전달 및 잡음 특성 분석)

  • Park, Jin-Hong
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.2
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    • pp.264-268
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    • 2009
  • In this paper, the two PCB design method results of boost converters are simulated with same circuit device parameters. One is modeled with microstrip structure and the other is modeled two layers structure without reference plane. Between devices of each circuit are routed 5 centimeters. When the switching frequency is operated 100kHz, the overshoot by signal reflection and the noise characteristics by frequency spectrum for the output voltage and current of the power switch is compared and analyzed using simulation.

A Study on the Sound Absorbing Performance of Parallel Perforated Plate Systems (병렬 다공판 시스템의 흡음성능에 관한 연구)

  • Hur, Sung-Chun;Lim, Jung-Bin;Ro, Sing-Nam;Lee, Dong-Hoon
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2002.11b
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    • pp.902-907
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    • 2002
  • An equivalent electroacoustic circuit approach of estimating the sound absorption coefficient for parallel perforated plate system is proposed. The proposed approach is validated by comparing the calculated absorption coefficients of a parallel single layer perforated plate system with the values measured by the two-microphone impedance tube method for various porosity and the number of perforated plate. The sound absorbing performances of parallel and series perforated plate systems are compared and discussed from a standpoint of frequency bandwidth with sound absorption. The proposed approach is further extended to the parallel double layer perforated plate system.

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High Sensitivity 3-axis Actuator for Slim Optical Disc Drive (슬림광디스크드라이브를 위한 고감도 3축구동 액추에어터)

  • Cheong, Young-Min;Lee, Jin-Won;Kim, Kwang
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2002.11b
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    • pp.1000-1003
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    • 2002
  • For high density optical storage, there should be a high NA objective lens and a shorter wavelength laser diode. To secure the disc tilt margin related to the coma aberration, moreover, it's difficult to apply the tilt compensation mechanism into the portable PC. In this paper, we proposed the 3-axis asymmetry pickup actuator with high efficiency symmetric magnetic circuit, which consisted of the top cover type inner yoke for high magnetic flux density, the coil stack unit for the 3-axis independent operation and vertically polarized magnets. This newly suggested actuator features DVD-RAM recording, we achieved the high focus & track AC sensitivity and the greatly stabilized system.

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Dynamics Modeling of Beams with Shunted Piezoelectric Elements (압전 공진 션트회로가 부착된 빔의 동적 모델링)

  • Park, Chul-H.;Park, Hyun-C.
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2002.11b
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    • pp.228-233
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    • 2002
  • General modeling of a resonant shunting damper has been made from piezoelectric sensor/actuator equation. It is found that an additional damping, which is augmented to a system, is generated by the shunt damping effect. The transfer function of the tuned electrical absorber is derived for both series and parallel shunt circuit. The governing equations and associated boundary conditions are derived using Hamilton's Principle. The shunt voltage equation is also derived from the charge generated in PZT due to beam vibration. The frequency response function of the obtained mathematical model is compared with that of the tuned electrical absorber and experimental work. The vibration amplitude is reduced about 15 dB at targeted second mode frequency.

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Design Methodologies for Reliable Clock Networks

  • Joo, Deokjin;Kang, Minseok;Kim, Taewhan
    • Journal of Computing Science and Engineering
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    • v.6 no.4
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    • pp.257-266
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    • 2012
  • This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

Analysis on Conductive Noise of High-Speed Train Including Pantograph Detachment (이선현상을 포함한 고속철도차량의 전도성 잡음 해석)

  • Lee, Sung-Gyen;Cho, Young-Maan;Ko, Kwang-Cheol
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.27 no.12
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    • pp.87-92
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    • 2013
  • In high-speed train, the EMI is generated by pantograph detachment and switching device of motor-block. Especially, the conductive noise flows through rail as return feeder influences unintended results to sub-station, transformer, etc. These phenomena were investigated by PSIM circuit analysis tool and each part of railway system is modeled by circuit elements and switching devices. Consequently, the distorted wave in return feeder current occurs by the high speed switching frequency, and the overvoltage is applied by the pantograph detachment. Also the distortion of return current is high in starting point and it decreases from the proximity of a starting point ro the end of terminal.

Design of ALGaAs/GaAs HBT CML Logic Circuit (ALGaAs/GaAs HBT CML 논리 회로 설계)

  • 최병하;김학선;김은로;이형재
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.17 no.5
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    • pp.509-520
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    • 1992
  • AIGaAs /GaAs HBT OR /NOR gate. which can be used for high speed digital system was designed. Equivalent circuit parameters of HBT were obtained from Gummel-Poon's model and direct extraction method. Simulation results with PSPI CE showed that propagation delay time and cutoff toggle frequency of designed gate were 25ps and 200Hz, respectively. the designed gate exhibited superior properties to the recently reported HBT ECL and MESFET SCFL when considering the fan-out characteristics and noise margin.

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A Design of High Resolution Temperature Measurement System Using Digital Signal Processor (디지털 신호처리기를 이용한 고분해능 온도측정 시스템 설계)

  • Kim, Tae-Hoon;Lim, Ju-Hyun;Kim, Duck-Young;Ko, Han-Woo;Kim, Sung-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.51 no.7
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    • pp.317-322
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    • 2002
  • This paper presents a linear temperature/voltage relation over a temperature range(0~100$^{\circ}C$) with high-resolution, reasonably god response linearity, reliability, and overall improved performance. A notable feature of the proposed method is that the whole temperature span is divided by 16 subbands thus the variation span of measured voltage is narrowed. Therefore noise characteristic has been improved. The output voltage is amplified after the uniformed DC voltage component is eliminated by offset. We proposed circuit using median value and mean value of digital signal in order to reduce the noise effect. The proposed circuit offers linear temperature/voltage conversion over a wide dynamic range using DSP(TMS320C31) and steinhart equation.

Extracting and Characterization of the Base Resistance based on Analysis of the Equivalent Noise Circuit for Common Collector (공통컬렉터 잡음등가회로 해석에 의한 베이스저항의 추출 및 특성)

  • Gu, Hoe-U;Lee, Gi-Yeong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.2
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    • pp.1-4
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    • 2000
  • We presented a method for extracting the base resistance r/sun bb/ based on analysis of the equivalent noise circuit for common collector. Measurements were conducted on devices with poly-emitter structure fabricated by BiCMOS process. Base resistance measurements have been performed for different base currents and structure. For low base current it is shown that the experimental data agree with theoretical expectations.

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VCO Design using NAND Gate for Low Power Application

  • Kumar, Manoj
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.5
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    • pp.650-656
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    • 2016
  • Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. In present work, VCO designs using the different combination of NAND gates with three transistors and CMOS inverter are reported. Three, five and seven stages ring VCO circuits are designed. Coarse and fine tuning have been done using two different supply sources. The frequency with coarse tuning varies from 3.31 GHz to 5.60 GHz in three stages, 1.77 GHz to 3.26 GHz in five stages and 1.27 GHz to 2.32 GHz in seven stages VCO respectively. Moreover, for fine tuning frequency varies from 3.70 GHz to 3.94 GHz in three stages, 2.04 GHz to 2.18 GHz in five stages and 1.43 GHz to 1.58 GHz in seven stages VCO respectively. Results of power consumption and phase noise for the VCO circuits are also been reported. Results of proposed VCO circuits have been compared with previously reported circuits and present circuit approach show significant improvement.