• Journal of the Semiconductor & Display Technology
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• v.9 no.2
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• pp.15-20
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• 2010

This paper deals with minimizing layout area of FPGA design. FPGAs are becoming increasingly important in the design of ASICs since they provide both large scale integration and user-programmability. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area-optimal embeddings for FPGA graphs in rectangles of several aspect ratios which solves the longest path problem in the constraint graph.

• The Journal of Korean Academy of Sensory Integration
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• v.14 no.1
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• pp.50-59
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• 2016

Objective : The goal of this study was to investigate neurological mechanism of emotional regulation and to examine the relationship between the regulation and sensory processing. Subjective : Emotional regulations are mainly processed in limbic system, particularly the basal-lateral group of amygdala takes on a major role in the regulations. The basal-lateral group of amygdala links to thalamus directly and/or indirectly which processes sensory information together. This sensory information connects to orbital and medial prefrontal cortex. Inadequate sensory processing may cause difficulties in emotional regulations and behaviors because of a circuit linking the amygdala, the thalamus, and the orbital and medial prefrontal cortex. These difficulties and impairments has been reported in neurological studies for children with ASD and ADHD. Conclusion : Neurological states are different between the normal children and children with ASD and ADHD and these represent various aspects in sensory processing, emotional regulations and behaviors. Thus, therapists working with children with ASD and ADHD need to understand mechanisms of sensory processing and emotional regulations in order to provide adequate treatments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.11
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• pp.1754-1766
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• 1993

The application of VXIbus system, an Industry standard, is rapidly spreading with its ability to offer the easiness of integration from GPIB and the fast data transmission from VMEbus system. Compared with VXIbus Register Based Device, VXIbus Message Based Device has a drawback In the aspect of speed. But it is possible to utilize high level ASCII commands to control a Message Based Device, therefore system integration is much easier with Message Based Device than with Register Based Device. And, the FFT analyzer is an instrument for signal analysis which can be inexpensively implemented to be fast and have high resolution. Its wide ability of analysis presents numerous application. So, it is necessary to apply VXIbus system to FFT analyzer. In this paper, the implementation of FFT analyzer is performed using a DSP module and by implementing all A/D conversion circuit and a control module which performs VXIbus interface. The device can be controlled by Slot0 Commender which supports VXIbus Shared Memory Protocol through VXIbus.

• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.1-10
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• 2009

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.855-862
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• 2003

This paper suggests the PIFA structure modified antenna in which short-circuit plate is located between planar element and ground plane, in order to solve the problem of narrow band of existing internal antenna, PIFA. It is also suggested that internal antenna has the perturbation in the patch to broaden the frequency bandwidth. It is possible that the antenna is installed into the mobile telephone with a low profile condition(h=0.015 λ) to use internally, and acquired desired bandwidth(5.2 %) through double resonance structure, remodeling the PIFA that is already well-known as an internal antenna. This paper investigated how characteristic is affected by the feeding point(Yf, Zf), short strip plate(Zs), short strip width(Ws), perturbation width(w), length(d), short plate height(h), dielectric($\varepsilon$$\_$r/) to be slim type antenna. It is compared with existing PIFA bandwidth, and is suggested pattern as the H.E plane. It is simulated using the Microwave Studio of the CST Inc. based on FIM(Finite Integration Method) method and analyzed antenna characteristic following the variation each parameters. The result proved the practical use of PIFA antenna by comparing the measured and simulated data of the antenna.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.210-215
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• 2017

We have developed the neuromorphic system that can work with the four-terminal Si-based synaptic devices and verified the operation of the system using simulation tool and printed-circuit-board (PCB). The symmetrical current mirrors connected to the n-channel and p-channel synaptic devices constitute the synaptic integration part to express the excitation and the inhibition mechanism of neurons, respectively. The number and the weight of the synaptic devices affect the amount of the current reproduced from the current mirror. The double-stage inverters controlling delay time and the NMOS with large threshold voltage ($V_T$) constitute the action-potential generation part. The generated action-potential is transmitted to next neuron and simultaneously returned to the back gate of the synaptic device for changing its weight based on spike-timing-dependent-plasticity (STDP).

• Journal of Power Electronics
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• v.14 no.2
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• pp.257-264
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• 2014

A novel converter-free AC LED driver that is highly resistant to the fluctuation of AC voltage is proposed in this study. By removing large passive components, such as the bulky capacitor and the large-value inductor, the integration of the driver circuit is enhanced while the driving current remains stable. The proposed circuit provides LED lamps with a driving current that can follow the sinusoid waveform to obtain a very high power factor (PF) and low total harmonic distortion (THD). The LED input current produced by this driving current is insensitive to fluctuations in the AC voltage. Users will thus not feel that LED lamps are flashing during the fluctuation. Experiment results indicate that the proposed system can obtain PF of 0.999 and THD as low as 3.3% for a five-string 6 W LED load under 220 V at 50 Hz.

• Fashion & Textile Research Journal
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• v.18 no.3
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• pp.363-373
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• 2016

This study aims to develop an all-fabric integrated smart jacket in order to create a temperature-regulating system based on a user experience design. For this research, previous research technologies of a textile switch interface and a temperature-regulating system were utilized and a unifying technology for the all-fabric integrated smart jacket was developed which can provide the appropriate temperature environments to the human body. A self-heating textile was applied at the areas of the back and hood in the final tested jacket, and an embroidery circuit was developed in the form of a rectangle in the back and in both ears of the hood, taking into account the pattern of the jacket part where it was be applied and the embroidery production method. The textile switch interface was designed in a three-layer structure: an embroidery circuit line in a conductive yarn, an interval material, and a conductive sensing material, and it was made to work with the input and output sensors through the multiple input method. After the all-fabric integrated smart jacket was produced according to the pattern, all of the textile band lines for transmission were gathered and connected with a miniature module for controlling temperature and then integrated into the inside of the left chest pocket of the jacket. After the users put on this jacket, they were asked to assess the wearing satisfaction. Most of them reported a very low level of irritation and discomfort and said that the jacket was as comfortable as everyday clothing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2267-2272
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• 2009

The six-port direct conversion receiver front-end that is comprised of a carrier recovery and a phase shifter, which gets the same structure with six-port phase correlator using the multi-layer coupled line, was designed and fabricated in this paper. The six-port element that is comprised of the power divider and the hybrid coupler is designed by multi-layer coupled line structure. The multi-coupled structure is utilized as the basic structure in receiver phase correlator, carrier recovery circuit and phase shifter. The receiver front-end with the same multi-layer coupled line structure for the receiver elements shows the simple structure and no difficulty in integration. The fabricated multi-layer coupled six-port receiver front-end re-generates the carrier signal with a constant phase and demodulates the PSK transmission signal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.1-10
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• 2008

In this paper, we describe a design of a 128bit MRAM based on a new switching architecture which is Local Field Switching(LFS). LFS uses a local magnetic field generated by the current flowing through an MTJ. This mode reduces the writing current since small current can induce large magnetic field because of close distance between MTJ and the current. It also improves the cell selectivity over using conventional MTJ architecture because it doesn't need a digit line for writing. The MRAM has 1-Transistor 1-Magnetic Tunnel Junction (IT-1MTJ) memory cell structure and uses a bidirectional write driver, a mid-point reference cell block and a current mode sense amplifier. CMOS emulation cell is adopted as an LFS-MTJ cell to verify the operation of the circuit without the MTJ process. The memory circuit is fabricated using a $0.18{\mu}m$ CMOS technology with six layers o) metal and tested on custom board.