• Korean Journal of Agricultural Science
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• v.48 no.4
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• pp.703-718
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• 2021

An irrigation monitoring system is an efficient approach to save water and to provide effective irrigation scheduling for rice cultivation in desert soils. This research aimed to design, fabricate, and evaluate the basic performance of an irrigation monitoring system based on information and communication technology (ICT) for rice cultivation under drip and micro-sprinkler irrigation in desert soils using a Raspberry Pi. A data acquisition system was installed and tested inside a rice cultivating net house at the United Arab Emirates University, Al-Foah, Al-Ain. The Raspberry Pi operating system was used to control the irrigation and to monitor the soil water content, ambient temperature, humidity, and light intensity inside the net house. Soil water content sensors were placed in the desert soil at depths of 10, 20, 30, 40, and 50 cm. A sensor-based automatic irrigation logic circuit was used to control the actuators and to manage the crop irrigation operations depending on the soil water content requirements. A developed webserver was used to store the sensor data and update the actuator status by communicating via the Pi-embedded Wi-Fi network. The maximum and minimum average soil water contents, ambient temperatures, humidity levels, and light intensity values were monitored as 33.91 ± 2 to 26.95 ± 1%, 45 ± 3 to 24 ± 3℃, 58 ± 2 to 50 ± 4%, and 7160-90 lx, respectively, during the experimental period. The ICT-based monitoring system ensured precise irrigation scheduling and better performance to provide an adequate water supply and information about the ambient environment.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.10
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• pp.895-903
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• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.

• Journal of the Korea Institute of Military Science and Technology
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• v.26 no.3
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• pp.227-233
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• 2023

In this paper, to substitute the existing TWTA(Travailing Wave Tube Amplifier) component in small radar system, we developed the Ku band SSPA(Solid-State Power Amplifier) based on the fabrication of power MMIC (Monolithic Microwave Integrated Circuit) chips. For the development of the 500 W SSPA, the 40 W-grade power MMIC was designed by ADS(Advanced Design System) at Keysight company with UMS GH015 library, and was processed by UMS foundry service. And 70 W main power modules were achieved the 2-way T-junction combiner method by using the 40 W-grade power MMICs. Finally, the 500 W SSPA was fabricated by the wave guide type power divider between the drive power amplifier and power modules, and power combiner with same type between power modules and output port. The electrical properties of this SSPA had 504 W output power, -58.11 dBc spurious, 1.74 °/us phase variation, and -143 dBm/Hz noise level.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.465-471
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• 2023

This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

• Journal of Advanced Navigation Technology
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• v.27 no.6
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• pp.849-854
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• 2023

In this paper, a high-efficiency power amplifier was designed by applying the operating point Class J using LDMOS(laterally diffused metal oxide semiconductor) and optimizing the output matching circuit so that the second harmonic impedance becomes the reactance impedance. The designed power amplifier has a frequency of 108 ~ 110 MHz, Characteristics of PAE(power added efficiency) is 71.5% at P_SAT output (54.5 dBm), 55.5% at P_1dB output (51.5 dBm), and 24.38% at 45 dBm. The CSB(carrier with sideband) amplifier, which is the reference signal in the spatial modulation method, has an operating output of 45 dBm ~ 35 dBm, and linear SDM(sum in the depth of modulation) characteristics(40% ± 0.3%) were obtained. We measure the characteristics in amplitude modulation according to the bias operating point of the power amplifier for CSB and propose the optimal operating point to obtain linear modulation characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.2
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• pp.175-181
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• 2024

In electrical power substations, bulky iron-core potential transformers (PTs) are installed in a tank of gas-insulated switchgear (GIS) to measure system voltages. This paper proposed a low-power voltage transformer (LPVT) that can replace the conventional iron-core PTs in response to the demand for the digitalization of substations. The prototype LPVT consists of a capacitive voltage divider (CVD) which is embedded in a spacer and an impedance matching circuit using passive components. The CVD was fabricated with a flexible PCB to acquire enough insulation performance and withstand vibration and shock during operation. The performance of the LPVT was evaluated at 80%, 100%, and 120% of the rated voltage (38.1 kV) according to IEC 61869-11. An accuracy correction algorithm based on LabVIEW was applied to correct the voltage ratio and phase error. The corrected voltage ratio and phase error were +0.134% and +0.079 min., respectively, which satisfies the accuracy CL 0.2. In addition, the voltage ratio of LPVT was analyzed in ranges of -40~+40℃, and a temperature correction coefficient was applied to maintain the accuracy CL 0.2. By applying the LPVT proposed in this paper to the same rating GIS, it can be reduced the length per GIS bay by 11%, and the amount of SF6 by 5~7%.

• Journal of IKEEE
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• v.28 no.1
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• pp.33-37
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• 2024

In this paper, we report the design and the measurement of a X-band low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) using a 0.25 ㎛ gate length microstrip GaN-on-SiC high electron mobility transistor (HEMT) technology. The developed X-band GaN-based LNA MMIC achieves small signal gain of 22.75 dB ~ 25.14 dB and noise figure of 1.84 dB ~ 1.94 dB in the desired band of 9 GHz to 10 GHz. Input and output return loss values are -11.36 dB ~ -24.49 dB and -11.11 dB ~ -17.68 dB, respectively. The LNA MMIC can withstand 40 dBm (10 W) input power without performance degradation. The chip dimensions are 3.67 mm × 1.15 mm. The developed GaN-based LNA MMIC is applicable to various X-band applications.

• Computers and Concrete
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• v.33 no.4
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• pp.425-443
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• 2024

Floods are among the most common natural hazards in urban areas. To mitigate the problems caused by flooding, unstructured data such as images and videos collected from closed circuit televisions (CCTVs) or unmanned aerial vehicles (UAVs) have been examined for flood management (FM). Many computer vision (CV) techniques have been widely adopted to analyze imagery data. Although some papers have reviewed recent CV approaches that utilize UAV images or remote sensing data, less effort has been devoted to studies that have focused on CCTV data. In addition, few studies have distinguished between the main research objectives of CV techniques (e.g., flood depth and flooded area) for a comprehensive understanding of the current status and trends of CV applications for each FM research topic. Thus, this paper provides a comprehensive review of the literature that proposes CV techniques for aspects of FM using ground camera (e.g., CCTV) data. Research topics are classified into four categories: flood depth, flood detection, flooded area, and surface water velocity. These application areas are subdivided into three types: urban, river and stream, and experimental. The adopted CV techniques are summarized for each research topic and application area. The primary goal of this review is to provide guidance for researchers who plan to design a CV model for specific purposes such as flood-depth estimation. Researchers should be able to draw on this review to construct an appropriate CV model for any FM purpose.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.1-5
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• 2024

This paper presents a crystal-less reference clock recovery (CR) frequency synthesizer with compensation designed for Bluetooth Low Energy (BLE) Smart-tag applications, operating at frequencies of 32, 72, and 80MHz. In contrast to conventional frequency synthesizers, the proposed design eliminates the need for external components. Using a single-ended antenna to receive a minimal input power of -36dBm at a 2.4GHz signal, the CR synthesizes frequencies by processing the RF signal received through a Low Noise Amplifier ( L N A ) . This approach allows the system to generate a reference clock without relying on a crystal. The received signal is amplified by the LNA and then input to a 16-bit ACC (Automatic Clock Compensation) circuit. The ACC compares the frequency of the received signal with the oscillator output signal, using the synthesis of a 32MHz reference clock through a frequency compensation method. The oscillator is constructed using a Ring Oscillator (RO) with a Frequency Divider, offering three different frequencies (32/72/80MHz) for various system components. The proposed frequency synthesizer is implemented using a 55-nm CMOS process.

• Journal of IKEEE
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• v.28 no.3
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• pp.445-450
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• 2024

This paper presents a varactor-less voltage-controlled oscillator (VCO) at W-band (75-110 GHz) with a compact size in a 0.15-㎛ GaAs pHEMT technology. For varactor-less frequency tuning, an inductive tuning circuit is employed. An active inductor is realized by the common-gate stage with gate termination and shows a wide tuning range with a high quality factor (Q-factor) compared with the conventional varactor diode. Colpitts topology with source feedback is employed for the oscillation core of the VCO. The varactor-less VCO exhibits a measured tuning range of 5.8 % and peak output power of 5.7 dBm at 88 GHz while the 146 mW of dc power is dissipated. Due to compact layout design, the chip size is only 0.48 mm².