• Journal of the Korea Computer Industry Society
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• v.7 no.3
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• pp.205-215
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• 2006

In this paper, a method how to make Programmable Logic Array (PLA) design and inspection of circuit relative to recent 64bit microprocessor simple and easy was discussed. A design method using Random Access Memory (RAM), Read Only Memory (ROM) and PLA has been settled down in Very Large Scale Integrated Circuit (VLSI) and logical design, modifying circuit and inspection are easy in PLA so it holds fairly good advantages in the aspect of performance and cost. It is expected PLA will also occupy an important position as a basic factor in designing VLSI in the future.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.1010-1018
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• 1988

This paper proposes a MOS circuit extractor which extracts a netlist from the hierarchical mask information, for the verification tools. To utilize the regularity and the simple representation of the hierarchical circuit, and to reduce the debug cycle of design, verification, and modification, we propose a hierarvhical and incremental circuit extraction algorithm. In flat circuit extraction stage, the multiple storage quad tree is used as an internal data structure. Incremental circuit extraction using the hierarchical structure is made possible, to reduce the re-extraction time of the modified circuit.

• Journal of information and communication convergence engineering
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• v.6 no.1
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• pp.43-46
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• 2008

This paper proposes an advanced test circuit for detecting the connectivity between a drum ring of laser printer and PCB. The detection circuit of charge sharing is proposed, which minimizes the influences of internal parasitic capacitances. The test circuit is composed of precharge circuit, analog comparator, level shifter. Its functional operation is verified using $0.6{\mu}m$ 3.3V/40V CMOS process parameter by HSPICE. Access time is100ns. Layout of the drum contact test circuit is $465{\mu}m\;{\times}\;117{\mu}m$.

• Journal of Advanced Navigation Technology
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• v.12 no.3
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• pp.255-262
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• 2008

In this paper, we developed the circuit and part information maintenance system based on JSP (Java Server Page) web server using web browser. Designers can easily search part information and register the new components or parts, and this system is linked to the EDA (Electronic Design Automation) system to be applicable to the circuit and part schematics in real time. Therefore, EDA system part library managed by individual designers are integrated into the web-based maintenance system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• Korean Institute of Interior Design Journal
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• v.17 no.3
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• pp.59-67
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• 2008

This study aims to find out the characteristics and the type classification of contemporary public libraries in terms of browsing circuit. In so doing, it is to analyze 21 recently built libraries by using the browsing circuit, the spatial depth and the spatial layout. The study makes use of codes derived from the concept of 'Classification' and 'Frame' suggested by a pedagogist, Basil Bernstein. As a result, it shows that two codes are phased in overseas cases. In other words, one type is a lower depth of space and a high rate of rings with the multi-layer circuits and the three-dimensional circuit of multi-centered. the other type is the higher depth of space and a low rate of rings with the single-layer circuit and the multi-layer circuit of single-centered. In domestic cases, 4 types are shown. The characteristics of layout are seen as a radial shape and the rate of rings is lower than the overseas cases. It can be said that these results are a transitional phenomenon. For browsing circuit, domestic public libraries would be adapted to the three-dimensional circuit of multi-centered, a lower depth of space and a high rate of rings. By instructions of this plan, the real meaning of a public library will be come true.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.106-110
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• 2005

In this paper, LED traffic signal lamp's operating circuit using Flyback converter and PFC IC has been presented. Most power conversion circuits use PFC IC for Power Factor Correction. The design parameter's value of Flyback converter has been proposed and the error amplifier which regulates the output voltage has been designed Besides, the under voltage protection circuit and the over voltage protection circuit for protecting the operating circuit kin unbalance of common electric power source and the temperature compensation circuit for fixed optical output power have been proposed.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.406-409
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• 2008

This paper presents the integrated magnetic circuit designing method for phase shift full bridge(PSFB) converter. The integrated magnetic circuit is implemented on redesigned of EI core. The transformer windings are located on center leg and the two inductors are located on the outer legs with air gap. Based on the equivalent circuit model, the principle of operation of the PSFB converter is explained. The operation and performance of the proposed circuit are verified on a 1.2 kW prototype converter. The analysis and design of the integrated magnetic circuit is verified through the experimental and simulation results.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.10
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• pp.727-732
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• 2004

TCXO is one of the most important component in communication systems. We present a analytic method approach to design the Temperature Compensated Circuit. The conventional method for extracting the circuit parameters, which are for thermistor, Colpitts and frequency control circuit is the trial and error correction. In this paper, we analyse the temperature compensating circuit to extract TCXO circuit parameter. In order to show the validity of this paper, we have designed and implemented the 10MHz TCXO. The fabricated TCXO shows 1ppm frequency drift characteristic over the temperature range of -40℃∼85℃.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.122-127
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• 2011

A general analysis of an aperture-coupled vertically mounted strip antenna is presented to examine its circuit characteristics. Based on the present analysis, an equivalent circuit model is developed, and an analytic or semi-analytic evaluation of the related circuit element values is described. The effects of structure parameters on the antenna characteristics were studied with the developed equivalent circuit, and the design curves were obtained. To check the validity of the proposed analysis and design theory, two C-band antennas (5.0 GHz and 4.5 GHz) were designed and fabricated. Their computed characteristics, derived from the proposed network analysis, were compared with the measurement and simulation results. The error of the current model in predicting the operating center frequency was less than 0.50 %. In addition, the observed bandwidth was found to be comparable to the conventional microstrip antennas. All the results fully validated the efficiency and accuracy of the proposed analysis and network model.