• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.1
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• pp.41-48
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• 2015

To deal with the emergency of the solitary aged people, we have developed a collapse-sensing phone, in which a collapse sensor, a GPS receiving chipset and a CDMA sending chipset are included. The general cellular phone is somewhat expensive communication device using sound and characters, but the collapse-sensing phone is a cheaper and popular version. If the collapse sensor recognizes a certain of collapse of the aged people, CDMA sending chipset will send the location of the phone which is received from satellite by GPS receiving chipset. In this paper, a collapse recognition algorithm which is developed by using much experimental data, will be introduced to explain how to recognize the real collapse from fast sitting or immediate standing after collapse. Once a true collapse is ecognized, the phone-ID and the coordinate will be sent to the server of administrative office via CDMA network. And the position of emergency will be displayed on the GIS with the rescue center.

• The KIPS Transactions:PartC
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• v.19C no.1
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• pp.39-46
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• 2012

In this paper, we propose a key distribution scheme for flexible chipset pairing conditional access system. Chipset pairing conditional access system is the implementation of CA (Conditional Access) module by using both embedded secure chip in a Set-Top Box(STB) and smartcard, and the secure chip embedded in a STB forms a secure channel between the smartcard and the STB. In short, it is the system that a smartcard outputs encrypted CW (Control Word) to the STB, and the STB decrypts an encrypted CW by using the embedded secure chip. The drawback of this chipset pairing conditional access system is that one smartcard is able to be used for only one specified STB since it is the system using the STB bound to a smartcard. However, the key distribution scheme proposed in this paper overcomes a drawback of current chipset pairing conditional access system by using Chinese Remainder Theorem(CRT). To be specific, with this scheme, one smartcard can be used for multiple, not single, STBs, and applied to current chipset pairing without great changes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.571-575
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• 2017

This paper presents a C-band bi-directional T/R chipset in $0.13{\mu}m$ TSMC CMOS technology for phased array antenna. The T/R chipset, which is a key component of phased array antenna, consists of a 6 bit phase shifter, a 6 bit step attenuator, and three bi-directional gain amplifiers. The phase shifter is controlled up to $354^{\circ}$ with $5.625^{\circ}$ phase step for precise beam steering. The step attenuator is also controlled up to 31.5 dB with 0.5 dB attenuation step for the side lobe level rejection. The LDO(Low Drop Output) regulator for stable 1.2 V DC power and the SPI(Serial Peripheral Interface) for digital control are integrated in the chipset. The chip size is $2.5{\times}1.5mm^2$ including pads.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.907-910
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• 2003

We have developed Logic Design Training Kit for studying, actual training, designing of FPGA(Xillinx) or CPLD(ALTERA CPLD), the Digital Logic Device. This training kit has 12 matrix keys, RS232 port for serial communication and uses LED array. six FND(Dynamic), LCD as display part. That is standard specification for digital logic training kit. Special point of this kit is that we make two logic device trainig kit. This two logic device kit have more smaller and simple architecture because only uses one chip. That chip already includes a lot of functions that need for training kit, such as : complex logic circuit needed the two kind of logic devices, 16 way of system clock deviding function, serial communication interrupt....etc. We called that one chip is Center Bridge Chipset ; Xillinx FPGA Spartan2. User can select between using one device of FPGA or CPLD, or uses both them. Because of, Center Bridge Chipset has profitable architecture. it can work as Logic Device's networking with Master-Slave connection When using both logic devices.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.33-41
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• 2014

This paper presents a IEEE1588 based clock synchronization technique for a sRIO (Serial RapidIO) network which is applied to a submarine system. Clock synchronization plays a key role in the success of a networked embedded system. Recently, the IEEE1588 algorithm making use of dedicated chipset has been widely used for the synchronization of various industrial applications. However, there is no chipset available for the sRIO network that can offer many advantages, such as low latency and jitter. In this paper, the IEEE1588 algorithm for a sRIO network is implemented using only software without any dedicated chipset. The proposed approach is verified with experimental setup.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.1343-1346
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• 2005

위치기반서비스 시스템에서 가장 기본이 되는 요소는 사용자의 위치를 정확히 측정하는 것이다. 측위 시스템은 옥외용과 옥내용으로 구분될 수 있고, 옥외용은 GPS 기반 시스템이 가장 일반적이다. 본 논문은 SiRF StarⅡ chipset을 이용하여 전자캠퍼스를 위한 옥외용 측위시스템 구현 사례를 소개한다. 전자캠퍼스의 특징으로 적용 영역이 비교적 협소하다는 것과 따라서 좀 더 정확한 측정 방법이 필요하다는 것을 들 수 있다. 본 논문은 RADAR 방식을 사용하여 오차를 줄일 수 있다는 것과 사용자 추적 방법 구현 사례를 보인다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.395-396
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• 2006

본 논문에서는 얼굴 인식의 성능을 효율적으로 향상시키기 위하여 Discrete Cosine Transform (DCT)와 Principal Component Analysis(PCA)에 기반한 새로운 특징 추출 방법을 제안한다. 얼굴 영상의 공간 영역은 DCT를 이용하여 주파수 영역으로 변환되며, DCT 도메인에서 얼굴 영상이 갖는 고유한 주파수 특성을 최적화 하는 주파수 밴드 영역을 추출한다. 차원이 축소된 데이터는 PCA 를 이용하여 데이터의 변별력에 가장 적합한 얼굴의 특징을 추출하고 Nearest Neighbor Classification 을 통해 본인여부를 확인 한다. 실험 결과 제안된 방법은 데이터의 차원을 효과적으로 축소하면서 기존의 얼굴 인식 방법에 비해 높은 인식률 향상을 보였다.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1376-1379
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• 1996

In this paper a GPS receiver is developed using commercial chipsets. GP2010 RF front end and GP2021 Multi-channel correlator of GEC PLESSY are adapted in designing the receiver hardware. MC 68340 is used for controlling the correlator GP2021 and implementing the navigation processing. Also presented are some test results of the developed receiver whose software has an interrupt driven structure rather than common real-time kernel based structure.

• The Magazine of the IEIE
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• v.22 no.9
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• pp.92-103
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• 1995

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.147-155
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• 2002

This paper describes RF front-end transceiver chipset for the dual-mode operation of PCS-Korea and IMT-2000. The transceiver chipset has been implemented in a $0.25\mutextrm{m}$ single-poly five-metal CMOS technology. The receiver IC consists of a LNA and a down-mixer, and the transmitter IC integrates an up-mixer. Measurements show that the transceiver chipset covers the wide RF range from 1.8GHz for PCS-Korea to 2.1GHz for IMT-2000. The LNA has 2.8~3.1dB NF, 14~13dB gain and 5~4dBm IIP3. The down mixer has 15.5~16.0dB NF, 15~13dB power conversion gain and 2~0dBm IIP3. The up mixer has 0~2dB power conversion gain and 6~3dBm OIP3. With a single 3.0V power supply, the LNA, down-mixer, and up-mixer consume 6mA, 30mA, and 25mA, respectively.