• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• The Journal of the Convergence on Culture Technology
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• v.6 no.3
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• pp.427-430
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• 2020

The multi-channel analog signal to digital signal conversion is increasing in the field of IoT and medical measurement equipments. It has chip area and power consumption constraints to use a few single or 2_channel ADC for multi_channel application. This paper described to design and implement a proposed comb filter for multi-channel, 24bit ADC. The function of proposed comb filter is verified by matlab simulation and the FPGA test board. It was fabricated using SK Hynix 0.35㎛ CMOS standard process. The performance and chip size is compared with the existing design method that uses integrator/differentiator and FIR construction. The proposed comb filter is expected to use the IoT product and medical measurement equipments that require multi-channel, low power consumption and small hardware size.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.121-126
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• 2006

This paper report on the design and implementation of a 9.6kbps DSSS CDMA modem for a medium speed wireless link. The proposed modem provides a general purpose I/O interface with a microprocessor. The I/O interface consists of 8-bit data bus, chip enable, read/write, and interrupt pins. In transmit block, the 8-bit data delivered from the I/O interface buffer is converted to 9.6kbps serial data, which are spreaded into 76.8kcps with 8-bit PN code generated inside the modem by direct sequence method. An 8-bit training sequence is preceded in the data frame for data synchronization in receiver. In receiver block the PN code is synchronized from the received data spreaded to 76.8kcps and find the data timing from the 8-bit training sequence. We have used the Early-and-Late integration method. The modem has been implemented and verified using a Xilix FPGA board and has been fabricated as an ASIC CHIP through Hynir $0.25{\mu}m$ CMOS. The multiple accessing method is DSSS CDMA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.8
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• pp.765-768
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• 2015

In this paper, two ports feeding a microstrip patch antenna using a quadrature hybrid circuit was proposed to enhance the bandwidth for the global positioning system(GPS). The square patch was designed, and the probe feeding was applied. The quadrature hybrid chip circuit for two-port feeding was designed, and output ports that have a 90-degree phase difference feed to the patch antenna. The designed patch and quadrature hybrid circuit were implemented on an FR4 board, and were combined. The measurement of the bandwidth within a voltage standing wave ratio(VSWR) of 2: 1 and axial ratio(AR) in 3dB were 29 %BW(1,230~1,700 MHz) and 15.87 %BW(1,400~1,650 MHz), respectively. The peak gain at the GPS center frequency was measured at 2.75 dBi in an anechoic chamber.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.9-17
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• 2007

This paper shows an implementation of the baseband processor compliant with the IEEE 802.11a standard. Some innovative techniques are proposed to fulfill the mandatory requirements of the standard. For verification and analysis of this design, we use a Platform-based SoC (system on chip) environment. The entire system consists of test-board for the baseband processor chip and the SoC platform for implementing MAC (medium access control).

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.7
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• pp.1-12
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• 2014

This paper is proposed to design the new heat-sink apparatus for improving the heat transfer characteristics in the power LED chip, and results of the operation characteristics were discussed. The core design is that the soldering through-hole on the FR-4 PCB board is formed to the effective heat transfer. That is directly filled with Ag-nano materials, which shows the high thermal conductivity. The heat transfer medium consisting of Ag-nano materials is classified into two structures. Mediums are called as the heat slug and the multi-pin in this work. The heat of the high temperature generated from the LED chip was directly transferred to the heat slug of the one large size. And the accumulated heat from the heat slug was quickly dissipated by the medium of the multi-pin, which is the same body with the heat slug. This multi-pin was designed for the multi-dissipation of heat by increasing the surface areas with a little pins. Subsequently, the speed of the heat transfer with this new heat-sink apparatus is three times faster than the conventional heat-sink. Therefore, the efficiency of the illuminating light will be improved by adapting this new heat-sink apparatus in the large area's LED.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.4
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• pp.121-127
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• 2024

In this paper, FEM (Front-End Module) MMIC, a key component for the application of the satellite communication terminal transmission and reception module of the multi-phase array structure, was designed and verified as a single chip by designing the Power Amplifier (PA) and the Low Noise Amplifier (LNA). It was manufactured using the GaAs PP10 (100nm) process, a compound semiconductor process from Win-semiconductors, and the operating frequency band of 7.2-10.5GHz operation, output 1W, and noise index of 1.5dB or less were secured using a dedicated test board. The developed FEM MMIC can be used as a single chip, and the components PA and LNA can also be used as each device. The developed device will be used in various applications of Minsu/Gunsu using the X band and the localization of overseas parts.

• International Commerce and Information Review
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• v.8 no.4
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• pp.71-88
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• 2006

This article want to discuss on comparative research between CHIPS and Fedwire as the cross-border payment systems which America have and use at present. CHIPS is a New York-based automated private-sector clearing facility for large-dollar transfers. It is a central switch communication and settlement system whose 53 participating banks exchange same-day payment messages over dedicated communication lines linking each one to the CHIPS central computer. On January 22, 2001, CHIPS introduced immediate finality for payment released from the CHIPS queue. Unlike the Fedwire system, The CHIPS system is not a real-time gross settlement system. Instead, CHIPS is hybrid system that uses a computer program to select payment order in a queue for release to the receiving bank. CHIPS are governed by CHIPS Rules and Administrative Procedures. Fedwire system is a nationwide electronic fund-transfer system facilitating same-day transfers throughout the United States. It is a gross settlement system providing immediate credit to the receiving bank's master account. Communicating between a Federal Reserve Bank and Fedwire users can be either on-line or off-line. Fedwire transfers are governed by Subpart B of Regulation J, issued by the Federal Reserve Board, which incorporates U.C.C. Article 4A but preempts or supersedes any of its inconsistent provisions.

• Advances in Traditional Medicine
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• v.6 no.1
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• pp.34-38
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• 2006

The hot water extract of the seeds of Vernonia anthelmintica Kuntze (Compositae) in a dose of 10 ml/kg body weight of mice, showed significant analgesic activity on the hot plate analgesic method throughout the 4 h experimental period. The hole cross scores and the climbing out scores are of lower than the control animals. The hot water extract reduced the defecation in hole board study and significantly reduces the exploratory ambulation and head dipping behaviour. The seed also showed significant depressant activity on the exploratory ambulation of the open field scores. The drug decreased the spontaneous locomotion activity on brick-chip displacement method up to 45 min and also showed the ability to lessen the amphetamine induced hyperactivity up to 20 min. But it didn't show any effect on pentobarbital induced sleeping time test. The extract reduced gastrointestinal motility.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.2
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• pp.135-140
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• 2008

In this paper, the spiral antenna with the center frequencies of 315MHz, 433MHz, and 447MHz for RKE system of a vehicle is designed on PCB. The antenna is microstrip line-fed, and applied PIFA concept near the feeding part to easily tune center frequency and input impedance. The PIFA-type spiral antenna with the size of $30mm{\times}20mm$ is designed on printed PCB by considering the effect of circuits and components on PCB, ECU case and vehicle body. Also chip inductor inserted dual-band spiral antenna of 315MHz and 447MHz is designed. We found that the antenna designed on PCB satisfied the antenna specifications through measurement and field test.