• Journal of the Korean Society for Precision Engineering
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• v.19 no.9
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• pp.151-156
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• 2002

A new position correction method using four fiducials as reference points was developed and examined. It was aimed to calibrate nonlinear deformation by numerous error sources. A correlation for correction was derived from the geometric relationship between four fiducials and chip position. Compared with three points method, it exhibited more accurate correction, especially for inner area of a quadrilateral composed of four fiducial points. Its accuracy was found to be increased as fiducials moves outwardly within a printed circuit board (PCB) and/or as they form more rectangle-like shape As for arbitrarily nonlinear deformation, this method can be applied using more than five fiducials. In this case, local-area calibration is carried out by sectioning a board area into several rectangular are as.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.779-782
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• 1991

The design of a control language of mobile robot system for autonomous operations is explained in this paper. The on-board controller consists of one-chip microcontrollerbased system and communicates with the host computer. It decodes the received commands and controls the mobile robot. The control language is basically of interpreter type and is consisted of motion primitives and sensing primitives. The combinations of primitives are constructed for mobile robot operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.19-25
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• 2000

Dielectric polymer films produced from benzocyclobutene (BCB) formulations (CYCLOTENE＊ family resins) are known to possess many desirable properties for microelectronic applications; for example, low dielectric constant and dissipation factor, low moisture absorption, rapid curing on hot plate without reaction by-products, minimum shrinkage in curing process, and no Cu migration issues. Recently, BCB-based products for thick film applications have been developed, which exhibited excellent dissipation factor and dielectric constant well into the GHz range, 0.002 and 2.50, respectively. Derived from these properties, the applications are developed in: bumping/wafer level packaging, Ga/As chip ILD, optical waveguide, flat panel display, and lately in BCB-coated Cu foil for build-up board. In this paper, we review the relevant properties of BCB, then the application areas in bumping/wafer level packaging and BCB-coated Cu foil for build-up board.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1642-1646
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• 2011

In this paper, A Design of 2.45GHz and GPS antenna Integrated Board using Container security Device(ConTracer) for container cargo transportation is proposed and experimentally evaluate. Integrated antenna board include 2.4GHz chip and Ceramic GPS antenna is also consider the impact of RF interference based on simulation for applied to steel container. After a careful comparison and analysis a part of the container door for its best performance, We conduct tests to characterize. The proposed integrated antenna board is suitable for container cargo transportation application in steel container field.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.2
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• pp.1-6
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• 2005

This paper studies the OF-LED(Optical Fiber-LED) illuminated display board system for energy saving. The OF-LED illuminated display board system has PV module, batteries, charge 8t discharge system and dynamic full color display controller. Both maximum power point tracker (MPPT) and constant current & constant voltage controls (CCVC) are used to govern the charging system. This system. improves the charging efficiency of battery. The system is compact and operates only by PV except the rainy days when the sun is unfavorable. in the system display control and charging-discharging control by on-chip microprocessor are simultaneously carried out. To verify the unposed system, me simulation and experiment results show the operating characteristics with a laboratory prototype.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.185-191
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• 2006

DSRC((Dedicated Short Range Communication) is dedicated short range communication for wireless communications between RSE(Road Side Equipment) and OBE(On-Board Unit) within vehicle moving high speed. In this paper, we implemented 5.8GHz DSRC modem according to Korea TTA(Telecommunication Technology Association) standard and investigated implementation results and design process for SoC(System on a Chip) embedding ARM CPU which control overall signal and process arithmetic work. The SoC is implemented by 0.11um design technology and 480pins EPBGA package. In the implemented SoC ($Jaguar^{TM}$), 5.8GHz DSRC PHY(Physical Layer) modem and MAC are designed and included. For CPU core ARM926EJ-S is embedded, and LCD controller, smart card controller, ethernet MAC, and memory controller are designed as main function.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.10
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• pp.907-913
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• 2015

This work presents a method to predict the near magnetic field distribution on the digital switching circuit mounted on PCB using co-simulation of circuit and electromagnetic fields. The proposed method first obtains the normalized near field distribution by exciting the signal and power ports of the switching circuit using sinusoidal sources. Then the real near magnetic field distribution is determined by weighting the normalized field distribution using the current spectrum of the switching circuit. To confirm the proposed method, a switching IC with a ring oscillator and a output buffer is fabricated and measured in the form of chip-on-board. The surface magnetic field distribution is measured using a magnetic probe above the PCB and compared with the simulation results. Experimental results show the correspondence between simulation and measurement results within 10 dB up to fifth harmonics.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.343-350
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• 2016

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.