• Korean Journal of Computational Design and Engineering
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• v.5 no.2
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• pp.155-167
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• 2000

To be presented is two-dimensional chip-load analysis for cutting-load smoothing which is needed in unmanned machining and high speed machining of sculptured surfaces. Cutter-engagement angle and effective cutting depth are defined as chip-loads which are the geometrical measures corresponding to cutting-load while machining. The extreme values of chip-loads are geometrically derived in the line-line and line-arc-line blocks of the two-dimensional NC-codes. AFA(automatic feedrate adjustment) strategy for cutting-load smoothing is presented based on the chip-load trajectories.

• Korean Journal of Computational Design and Engineering
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• v.5 no.2
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• pp.175-183
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• 2000

Proposed in this paper is a model-bated AFA (automatic feedrate-adjustment) method for maintaining smooth cutting-loads (i.e., cutting-force) during 2D-profile milling. Before the cutting-force model was established, some assumptions were verified through a series of preliminary cutting experiments (The results found that the curving-force was independent of the cutting speed and the cutting action at the cutter bosom). From the data obtained during the main cutting experiments, a “chip-load/cutting-force model”representing the cutting-force as a function of the chip-load (i.e., effective cutting-depth) and a feedrate is proposed. Based on the model. an AFA scheme for maintaining smooth cutting-force by adjusting the feedrate (i.e., F-code) according to the changes in chip-load was proposed. To check the validity of the proposed AFA scheme. another set of cutting experiments was conducted by using feedrate-adjusted NC-data while monitoring the actual machining processes using an accelerometer. The experimental results showed that the proposed AFA-scheme was quite effective.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.4
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• pp.68-75
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• 2005

This paper presents a new method for the optimization of feed rate in sculptured surface machining. A NC verification model based on Z-map was utilized to obtain chip load according to feed per tooth. This optimization method can regenerate a new NC program with respect to the commanded cutting conditions and the NC program that was generated from CAM system. The regenerated NC program has not only the same data of the ex-NC program but also the updated feed rate in every block. The new NC data can reduce the cutting time and produce precision products with almost even chip load to the feed per tooth. This method can also reduce tool chipping and make constant tool wear.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.801-805
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• 2000

This paper presents a new method of tool path optimization. A NC verification model based Z-map was utilized to obtain chip load in feed per tooth. This developed software can regenerate a NC program from cutting condition and the NC program that was generated in CAM. The regenerated NC program has not only all same data of the ex-NC program but also the new feed rates in every block. The new NC data can reduce the cutting time and manufacture precision dies with the same chip load in feed per tooth. This method can also prevent tool chipping and make constant tool wear. This paper considered the effects of acceleration and deceleration in feed rate change.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1663-1667
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• 2003

This thesis is on tile development of LD(Laser Diode) chip tester and the control system based on graphical programming language(LabVIEW) to control the equipment. The LD chip tester is used to test the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the receiver(optic fiber) are very small. Therefore, in order to test each chip precisely, this tester needs high accuracy. However each motion part of the tester could not accomplish hish accuracy due to the limit of the mechanical performance. Hence. an image processing with machine vision was carried out in order to compensate for the error. and also a load test was carried out so as to reduce tile impact of load on chip while the probing motion device is working. The obtained results were within ${\pm}$5$\mu\textrm{m}$ error.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.1
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• pp.42-48
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• 2011

In this paper, a passive load-pull using a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) bare-chip in X-band is presented. To obtain operation conditions that characteristic change by self-heating was minimized, pulsed drain bias voltage and pulsed-RF signal is employed. An accuracy impedance matching circuits considered parasitic components such as wire-bonding effect at the boundary of the drain is accomplished through the use of a electro-magnetic simulation and a circuit simulation. The microstrip line length-tunable matching circuit is employed to adjust the impedance. The measured maximum output power and drain efficiency of the pulsed load-pull are 42.46 dBm and 58.7%, respectively, across the 8.5-9.2 GHz band.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2004.04a
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• pp.93-98
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• 2004

A reasonable analysis of cutting force in end milling may give much advantage to improvement of productivity and cutting tool life. In order to analyze cutting force, the cutting dynamics was modelled mathematically by using chip load, cutting geometry, and the relationship between cutting forces and the chip load. Specific cutting constants of the cutting dynamics model were obtained by average cutting forces, tool diameter, cutting speed, feed, axial depth, and radial depth of cut. The effects of the cutting conditions on the specific cutting force constants in milling were studied. The model is verified through comparisons of model predicted cutting forces with measured culling forces obtained from machining experiments

• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.4
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• pp.9-15
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• 2004

A reasonable analysis of cutting force in end milling may give much advantage to improvement of productivity and cutting tool life. In order to analyze cutting force, the cutting dynamics was modelled mathematically by using chip load, cutting geometry, and the relationship between cutting forces and the chip load. The specific cutting constants of the cutting dynamics model were obtained by average cutting forces, tool diameter, cutting speed, feed, axial depth, and radial depth of cut. The model is verified through comparisons of model predicted cutting forces with measured cutting forces obtained from machining experiments. The results showed good agreement and from that we could predict reasonably the cutting forces in end milling.