• ETRI Journal
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• v.27 no.5
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.43-48
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• 2002

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• Smart Media Journal
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• v.1 no.1
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• pp.27-35
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• 2012

In this paper, the performance analysis for multimedia video codec(MPEG-4, H.264) on on-chip network communication architecture is presented. The On-Chip Network (OCN) is the new communication architecture of multimedia SoC design that overcomes the limits of On-Chip Bus architecture by providing higher data traffic bandwidth, reusability and higher scalability. We compared the performance of MPEG-4, H.264 decoder based on-chip network and AMBA on-chip bus. Experimental results show that the performance of MPEG-4, H.264 based on on-chip network is improved over 33~56% compared to the design based on AMBA on-chip bus.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.271-275
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• 1995

Chip control is a major problem in automatic machining process, especially in finish operation. Chip breaker is one of the important factors to be determined for the scheme of chip control. As unbroken chips are grown, there deteriorate quality of the surface roughness and process automation can be carried out. In this study, to get rid of chip curling problem while turning internal hole, optimal chip breaker is selected form the experiment. The experiment is planned with Taguchi's method that is based on the orthogonal arrary of design factor. From the respose table, cutting speed, feedrate, depth of cut, and tool geometry are major factors affecting chip formation. Then, optmal chip breaker is selected and this is verified good enough for chip control from the experiment.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.57-57
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• 2000

The purpose of this paper is show that an chip mounter can be modeled by stochastic petri nets, and that the simulator to verify a fitness of the program to assemble. The chip mounter can be constructed by using the petri net class (CPetriNet) based on the object-oriented programming. By using this simulator, we can get the information about the description of motion of the chip mounter, and moreover, we can evaluate the productivity.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.154-159
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• 2003

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• Journal of the Semiconductor & Display Technology
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• v.14 no.3
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• pp.13-22
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• 2015

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.11
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• pp.28-34
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• 2011

In CDMA-based systems, recently, researches on chip-level equalization have been studied in order to improve receiving performance when supporting high-rate data services. In this paper, we propose Griffiths' algorithm based chip-level adaptive LMMSE equalizers for HSDPA MIMO systems using D-TxAA (dual stream transmit antenna array). First, we will derive two possible structures of Griffiths' algorithm based equalizer, and then compare their performance through computer simulations in various mobile channel environments.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.7 no.3
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• pp.118-125
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• 1998

Chip control is a major problem in automatic machining process, especially in finish turning operation. In this case, chip breaker is one of the important factors to be determined. As unbroken chips are grown. these deteriorate the surface roughness. and proces automation can not be carried out. In this study to get rid of chip curling problem while turning internal hole. optimal chip breaker is selected from the experiment. The experiment is planned with Taguchi's method that is based on the orthogonal arrary of design factors. From the response table. cutting speed, feedrate, depth of cut and tool geometry turn to be major factors affecting chip formation. Then, optimal chip breaker is selected. and this is verified as good enough for chip control from the experiment.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.12
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• pp.163-168
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• 2000

Once the chip has developed a mixed mode of side-curl and up-curl, it would generally curl to strike the tool flank. The development of the bending stresses and sheat in the chip would ultimately lead to chip failure. This paper approach this problem from a mechanics-based approach, by treating the chip as a 3-D elastic curved beam, and applying appropriate constraints and forces. The expressions for bending, shear and direct stresses are developed through an energy-based criterion. The location of the maximum stresses is also identified and explained for simulated test conditions.