• 제목/요약/키워드: Chip thickness

검색결과 274건 처리시간 0.031초

이원계 전해도금법에 의한 Sn-3.0Ag-0.5Cu 무연솔더 범핑의 정밀 조성제어 (Precise composition control of Sn-3.0Ag-0.5Cu lead free solder bumping made by two binary electroplating)

  • 이세형;이창우;강남현;김준기;김정한
    • 대한용접접합학회:학술대회논문집
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    • 대한용접접합학회 2006년도 춘계 학술대회 개요집
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    • pp.218-220
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    • 2006
  • Sn-3.0Ag-0.5Cu solder is widely used as micro-joining materials of flip chip package(FCP) because of the fact that it causes less dissolution and has good thermal fatigue property. However, compared with ternary electroplating in the manufacturing process, binary electroplating is still used in industrial field because of easy to make plating solution and composition control. The objective of this research is to fabricate Sn-3.0Ag-0.5Cu solder bumping having accurate composition. The ternary Sn-3.0Ag-0.5Cu solder bumping could be made on a Cu pad by sequent binary electroplating of Sn-Cu and Sn-Ag. Composition of the solder was estimated by EDS and ICP-OES. The thickness of the bump was measured using SEM and the microstructure of intermetallic-compounds(IMCs) was observed by SEM and EDS. From the results, contents of Ag and CU found to be at $2.7{\pm}0.3wt%\;and\;0.4{\pm}0.1wt%$, respectively.

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LCD Module내 COF Bending에 따른 Lead Broken Failure의 개선 (Improvement of COF Bending-induced Lead Broken Failure in LCD Module)

  • 심범주;최열;이준신
    • 한국전기전자재료학회논문지
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    • 제21권3호
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    • pp.265-271
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    • 2008
  • TCP(Tape Carrier Package), COG (Chip On Glass), COF(Chip On Film) are three methods for connecting LDI(LCD Driver IC) with LCD panels. Especially COF is growing its portion of market place because of low cost and fine pitch correspondence. But COF has a problem of the lead broken failure in LCD module process and the usage of customer. During PCB (Printed Circuit Board) bonding process, the mismatch of the coefficient of thermal expansion between PCB and D-IC makes stress-concentration in COF lead, and also D-IC bending process during module assembly process makes the level of stress in COF lead higher. As an affecting factors of lead-broken failure, the effects of SR(Solder Resister) coating on the COF lead, surface roughness and grain size of COF lead, PI(Polyimide) film thickness, lead width and the ACF(Anisotropic Conductive Film) overlap were studied, The optimization of these affecting manufacturing processes and materials were suggested and verified to prevent the lead-broken failure.

열공압 방식으로 구동되는 매세 유체 제어 시스템의 제작 및 특성 (Fabrications and Characteristics of Microfluidic Systems Actuated by Thermopneumatic Method)

  • 유종철;강치중;김용상
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제55권2호
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    • pp.88-92
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    • 2006
  • We present a microfluidic system with microvalves and a micropump that are easily integrated on the same substrate using the same fabrication process. The fabricated microfluidic system is suitable for use as a disposable device and its characteristics are optimized for use as a micro chemical analysis system (micro-TAS) and lab-on-a-chip. The system is realized by means of a polydimethylsiloxane (PDMS)-glass chip and an indium tin oxide (ITO) heater. We demonstrate the integration of the micropump and microvalves using a new thermopneumatic-actuated PDMS-based microfluidic system. A maximum pumping rate of about 730 nl/min is observed at. a duty ratio of 1 $\%$ and a frequency of 2 Hz with a fixed power of 500 mW. The measured power at flow cut-off is 500 mW for the microvalve whose channel width, depth and membrane thickness were 400 $\mu$m, 110 $\mu$m, and 320 $\mu$m, respectively.

Thermal Analysis and Optimization of 6.4 W Si-Based Multichip LED Packaged Module

  • Chuluunbaatar, Zorigt;Kim, Nam Young
    • 한국통신학회논문지
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    • 제39C권3호
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    • pp.234-238
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    • 2014
  • Multichip packaging was achieved the best solution to significantly reduce thermal resistance at the same time, to increase luminance intensity in LEDs packaging application. For the packaging, thermal spreading resistance is an important parameter to get influence the total thermal performance of LEDs. In this study, silicon-based multichip light emitting diodes (LEDs) packaged module has been examined for thermal characteristics in several parameters. Compared to the general conventional single LED packaged chip module, multichip LED packaged module has many advantages of low cost, low density, small size, and low thermal resistance. This analyzed module is comprised of multichip LED array, which consists of 32 LED packaged chips with supplement power of 0.2 W at every single chip. To realize the extent of thermal distribution, the computer-aided design model of 6.4 W Si-based multichip LED module was designed and was performed by the simulation basis of actual fabrication flow. The impact of thermal distribution is analyzed in alternative ways both optimizing numbers of fins and the thickness of that heatsink. In addition, a thermal resistance model was designed and derived from analytical theory. The optimum simulation results satisfies the expectations of the design goal and the measurement of IR camera results. tart after striking space key 2 times.

$BiNbO_4$세라믹스를 이용한 저역통과 필터에 관한 연구 (Experimental Fabrication of Low Pass Filter of $BiNbO_4$ Ceramics)

  • 고상기;김경용;김병호;최환
    • 한국전기전자재료학회논문지
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    • 제11권4호
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    • pp.281-287
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    • 1998
  • $BiNbO_4$ ceramics doped with 0.07wt% $V_2O_5$ and 0.03wt% CuO (BNC3V7) were sucessfully sintered at $900^{\circ}C$ through the firing process with Ag electrode. The BNC3V7 shows typically Dielectric constant of 44.3, Thermal Coefficient of resonance Frequency(TCF) of 2 ppm/$^{\circ} and $Qxf_o$ value of 22,000 GHz. The laminated chip Low Pass Filter (LPF) is very sensitive to chip processing parameters, was confirmed by the computer simulation as a function of Q(Quality factors), filter size, capacitor layer thickness, inductor pattern widths. The multilayer type LPF was fabricated by screen-printing with Ag electrode after tape casting and then compared with the simulated characteristics. The results show that characterization of band pass width was similar to that of designed ones.

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Simple and Cost-Effective Method for Edge Bead Removal by Using a Taping Method

  • Park, Hyeoung Woo;Kim, H.J.;Roh, Ji Hyoung;Choi, Jong-Kyun;Cha, Kyoung-Rae
    • Journal of the Korean Physical Society
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    • 제73권10호
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    • pp.1473-1478
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    • 2018
  • In this study, we have developed a simple and cost-effective method to prevent edge bead formation by covering the edge of a chip-level substrate with heat-resistant tape during patterning using SU-8. Edge beads are a fundamental problem in photoresists and are particularly notable in high-viscosity fluids and thick coatings. Edge beads can give rise to an air gap between the substrate and the patterning mask during UV exposure, which results in non-uniform patterns. Furthermore, the sample may break since the edge bead is in contact with the mask. In particular, the SU-8 coating thickness of the chip-level substrates used in MEMS or BioMEMS may not be properly controlled because of the presence of edge beads. The proposed method to solve the edge bead problem can be easily and economically utilized without the need for a special device or chemicals. This method is simple and prevents edge bead formation on the sample substrate. Despite the small loss in the taping area, the uniformity of the SU-8 coating is improved from 50.9% to 5.6%.

PDMS 블레이드 코팅법을 이용한 종이-기반 바이오센서칩 제작 (Fabrication of Paper-based Biosensor Chip Using Polydimethylsiloxane Blade Coating Method)

  • 정헌호;박차미
    • Korean Chemical Engineering Research
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    • 제59권1호
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    • pp.100-105
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    • 2021
  • 본 연구는 적은 비용으로 분석 장치 없이 질병 진단 및 경과를 모니터링할 수 있는 종이-기반 분석 장치(paper-based analytical device, PAD)를 제작하기 위해 polydimethylsiloxane (PDMS) 블레이드 코팅 방법을 제안하였다. PAD 디자인은 레이저 커팅 기술로 쉽게 몰드에 적용할 수 있으며, 제작된 몰드로 블레이드 코팅을 수행하여 완전한 소수성 장벽 형성에 필요한 조건을 확립하였다. 코팅 조건인 잉크의 두께와 종이와의 접촉시간에 따라 PDMS 소수성 장벽의 구조와 친수성 채널의 크기 변화를 분석하여 안정적으로 소수성 장벽을 형성할 수 있는 조건을 최적화하였다. 최적화된 방법을 바탕으로 PAD를 제작하여 특별한 분석기기 없이 단백질, 당, 메탈이온을 검출하여 바이오센서에 응용가능함을 증명하였다.

칩과 안테나 사이 연결부 보호를 위한 RFID 태그 안테나의 광대역 설계 (Wide Bandwidth RFID Tag Antenna Design for Protection of Connection Part between Chip and Antenna)

  • 이지철;민경식
    • 한국전자파학회논문지
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    • 제20권2호
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    • pp.154-160
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    • 2009
  • 본 논문은 칩과 안테나 사이의 연결부 보호를 위한 RFID 태그 안테나의 광대역 설계에 대해서 기술한다. 제안된 태그 안테나의 크기, 공진 주파수 그리고 대역폭은 각각 $53{\times}10{\times}1\;mm$, 900 MHz이고, -10 dB 이하에서 800 MHz($500{\sim}1,200\;MHz$)이다. 폴리에틸렌, 유리 그리고 실리콘과 같은 다른 비유전율을 가지는 유전체 매질들이 제안된 안테나와 칩의 연결부 보호를 위해 전체 하우징과 부분 하우징으로 적용되었다. 측정된 반사 손실과 방사 패턴은 계산 결과와 비교하여 잘 일치하였다. 하우징을 하지 않은 제안된 태그 안테나의 인식거리와 3 mm 두께를 가진 실리콘에 의해 전체적으로 하우징된 태그 안테나의 인식거리는 각각 약 5 m와 4 m로 관측되었다.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • 이강욱
    • 마이크로전자및패키징학회지
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    • 제22권2호
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

초정밀 엔드밀링 가공조건 최적화를 통한 금속상의 3차원 이미지 구현 (Realization of 3D Image on Metal Plate by Optimizing Machining Conditions of Ultra-Precision End-Milling)

  • 이재령;문승환;제태진;정준호;김휘;전은채
    • 한국정밀공학회지
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    • 제33권11호
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    • pp.885-891
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    • 2016
  • 3D images are generally manufactured by complex production processes. We suggested a simple method to make 3D images based on a mechanical machining technology in this study. We designed a tetrahedron consisted of many arcs having the depth of $100{\mu}m$ and the pitch of $500{\mu}m$, and machined them on an aluminum plate using end-milling under several conditions of feed-rate and depth of cut. The area of undeformed chip including depth of cut and feed-rate can predict quality of the machined arcs more precisely than the undeformed chip thickness including only feed rate. Moreover, a diamond tool can improve the quality than a CBN tool when many arcs are machined. Based on the analysis, the designed tetrahedron having many arcs was machined with no burr, and it showed different images when observed from the left and right directions. Therefore, it is verified that a 3D image can be designed and manufactured on a metal plate by end-milling under optimized machining conditions.