• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2002.07a
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• pp.333-338
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• 2002

인간 게놈 프로젝트가 지속적으로 진행됨에 따라 계속적으로 대량의 유전체 정보가 밝혀지고 있으며, 이미 밝혀진 유전체의 염기서열을 바탕으로 다양한 생물의 전체 유전자의 기능을 효율적으로 해석하는 기술의 개발이 요구되고 있다. 식물 게놈 프로젝트 또한 식량확보라는 단순하면서도 전략적인 차원에서 가장 절실히 요구되는 기본 과학기술 연구분야이다. (중략)

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.474-480
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• 2003

We designed and tested a new scan driver output stage. Compared to conventional CMOS structured scan driver IC′s, the new NMOSFET-only scan driver circuit can reduce the chip area and therefore, the chip cost considerably. We confirmed the circuit operation with open drain power NMOSFET IC′s by driving 2"PDP test panel. We defined critical device parameters and their optimization methods lot the best circuit performance.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2003.12a
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• pp.77-85
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• 2003

기 상용화되고 있는 소프트웨어/하드웨어 제품의 복제방지에 대한 강도가 부족하여 쉽게 락이 크랙될 뿐 아니라 복제방지의 기능을 수행할 수 없는 단점을 보안하여 본 논문은 세계적으로 가장 많이 사용하고 있는 암호알고리즘 중의 하나인 DES를 구조적으로 수정하고 키 길이를 확장하여 암호학적 강도를 개선한 E-DES(Extended DES)를 설계하고, 이를 하드웨어로 구현하기 위해서 시스템 설계 기술언어인 VHDL로 코딩하고, FPGA를 이용, test chip을 구현하여 성능테스트를 수행한 다음, 설계된 FPGA 칩을 ASIC으로 제작하여 강력한 암호알고리즘을 가진 보안칩을 설계한다.

• Journal of Korea Foundry Society
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• v.31 no.2
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• pp.60-65
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• 2011

Molten magnesium alloys and magnesium products are easily oxidized and burned when they are exposed to high temperature for manufacturing process and by accident. In order to solve these problems, CaO addition in magnesium alloys has been developed. The ignition resistance of CaO added Mg-3Al, Mg-6Al, and Mg-9Al Eco-Mg alloys were investigated in comparison with those of magnesium alloys without CaO. The ignition resistance was examined by three methods : DTA, furnace chip ignition test, and torch ignition test. DTA was carried out for obtaining quantitative ignition temperature data with respect to specimen geometry and test environment; the furnace ignition test for burr and chip ignition temperature data; and the torch test for ignition temperature data for manufactured products. The ignition resistance of magnesium alloys under all conditions greatly increased by CaO addition.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.106-113
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• 2014

Recently, to reduce test cost by efficiently compressing test patterns for SOCs(System-on-a-chip), different compression techniques have been proposed including the FDR(Frequency-directed run-length) algorithm. FDR is extended to EFDR(Extended-FDR), SAFDR(Shifted-Alternate-FDR) and VPDFDR(Variable Prefix Dual-FDR) to improve the compression ratio. In this paper, a frequency-ordered modification is proposed to further augment the compression ratios of FDR, EFDR, SAFRD and VPDFDR. The compression ratio can be maximized by using frequency-ordered method and consequently the overall manufacturing test cost and time can be reduced significantly.

• Progress in Superconductivity
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• v.4 no.1
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• pp.74-79
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• 2002

High-speed probe made to test single flux quantum(SFQ) circuits was comprised of semi-rigid coaxial cables and microstrip lines. The impedance was set at 50 $\Omega$to carry high-speed signals without much loss. To do performance test of high-speed probe, we have attempted to fabricate a test chip which has a coplanar waveguide(CPW) structure. Electromagnetic simulation was done to optimize the dimension of CPW so that the CPW structure has an impedance of 50$\Omega$, matching in impedance with the probe. We also used the simulation to investigate the effect of the width of signal line and the gap between signal line and ground plane to the characteristics of CPW structure. We fabricated the CPW structure with a gold film deposited on Si wafer whose resistivity was above $1.5\times$10$_4$$\Omega$.cm. The magnitudes of S／sub 21／ of CPW at 6 ㎓ in simulations and in the actual measurements done with a network analyzer were: -0.1 ㏈ and -0.33 ㏈ (type A),-0.2 ㏈ and -0.48 ㏈ (type B), respectively. Using the test chip, we have successfully tested the performance of high-speed probe made for SFQ circuits. The probe showed the good performance overthe bandwidth of 10 ㎓.

• Nuclear Engineering and Technology
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• v.50 no.8
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• pp.1298-1305
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• 2018

The use of System-on-Chip (SoC) solutions in the design of on-board data handling systems is an important step towards further miniaturization in space. However, the Total Ionizing Dose (TID) and Single Event Effects (SEE) characterization of these complex devices present new challenges that are either not fully addressed by current testing guidelines or may result in expensive, cumbersome test configurations. In this paper we report the test setups, procedures and results for TID testing of a SoC microcontroller both using standard $^{60}Co$ and low-energy protons beams. This paper specifically points out the differences in the test methodology and in the challenges between TID testing with proton beam and with the conventional gamma ray irradiation. New test setup and procedures are proposed which are capable of emulating typical mission conditions (clock, bias, software, reprogramming, etc.) while keeping the test setup as simple as possible at the same time.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Korean Journal of Food Science and Technology
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• v.29 no.4
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• pp.635-640
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• 1997

The oxidative stability of the potato chip prepared with canola oil fortified with antioxidnats was studied to explore the possibility of substituting it for imported frying fats and oils. BHT, BHA, TBHQ and silicone were added to the oil at a level of 0.02% and 10 ppm, respectively. Potato chip samples were prepared in a commercial scale and stored at $25.0{\pm}0.5^{\circ}C$ for 5 months. The oxidative stability of the extracted oils from potato chips during storage was estimated on the basis of some their physico-chemical changes, such as acid values, peroxide values, iodine values, ansidine values, fatty acid composition of the oils. An organoleptic test for the flavor of the samples was also performed. The oxidative stability of the samlpes was estimated on the basis of the changes of the parameter values. The effectiveness of the antioxidants was in the order of canola oil+TBHQ (0.02%)+silicone (10 ppm) > canola oil+TBHQ (0.02%) > canola oil+BHA (0.02%)+silicone (10 ppm) > canola oil+BHT (0.02%)+silicone (10 ppm) > canola oil+BHA (0.02%) > canola oil+BHT (0.02%) > canola oil. The antioxidant effect of canola oil+TBHQ (0.02%)+silicone (10 ppm) was more salient than any other antioxidant used in the potato chip.

• Journal of Welding and Joining
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• v.25 no.2
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• pp.37-42
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• 2007