• Journal of Surface Science and Engineering
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• v.36 no.2
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• pp.214-225
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• 2003

Trends in microelectronics packages such as low cost, miniaturization, high performance, and high reliability made area array interconnecting technologies including flip chip, CSP (Chip Scale Package) and BGA (Ball Grid Array) mainstream technologies. Underfill technology is used for the reliability of the area array technologies, thus electronics packaging industry regards it as very important technology In this paper, the underfill technology is reviewed and the recent advances in the underfill technology including new processes and materials are introduced. These includes reworkable underfills, no-flow underfills, molded underfills and wafer - level - applied underfills.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.119-123
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• 2001

In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.10
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• pp.183-190
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• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.15-16
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• 2008

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.821-822
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• 2011

• Journal of the Korean Chemical Society
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• v.54 no.5
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• pp.594-602
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• 2010

Since the requirement of the high density integration and thin package technique of semiconductor have been increasing, the main package type of semiconductor will be a chip scale package (CSP). The changes of diffusion coefficient and moisture content ratio of epoxy resin systems according to the change of liquid type epoxy resin and fillers for CSP applications were investigated. The epoxy resins used in this study are RE-304S, RE310S, and HP-4032D, and Kayahard MCD as hardener and 2-methylimidazole as catalyst were used in these epoxy resin systems. The micro-sized and nano-sized spherical type fused silica as filler were used in order to study the moisture absorption properties of these epoxy molding compound (EMC) according to the change of filler size. The temperature of glass transition (Tg) of these EMC was measured using Dynamic Scanning Calorimeter (DSC), and the moisture absorption properties of these EMC according to the change of time were observed at $85^{\circ}C$ and 85% relative humidity condition using a thermo-hygrostat. The diffusion coefficients in these EMC were calculated in terms of modified Crank equation based on Ficks' law. An increase of diffusion coefficient and maximum moisture absorption ratio with Tg in these systems without filler can be observed, which are attributed to the increase of free volume with Tg. In the EMC with filler, the changes of Tg and maximum moisture absorption ratio with the filler content can be hardly observed, however, the diffusion coefficients of these systems with filler content show the outstanding changes according to the filler size. The diffusion via free volume is dominant in the EMC with micro-sized filler; however, the diffusion with the interaction of absorption according the increase of the filler surface area is dominant in the EMC with nano-sized filler.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.24 no.4
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• pp.448-454
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• 2015

In this paper, the band structural design that is typically in a line was arranged in a ring shape, so as to configure the high power LED lighting in such a way as to form a concentrated light distribution angle of less than 15 degrees. The parabolic aluminized reflector PAR38 that facilitates design using area and the area of the optical system to the same extent, applied a multiple light-source condenser lens optical system for the control of integration. The LED used here implemented a single linear light source using ans LED module with ans LED, flip-chip chip-scale package. The optical system was designed based on the energy star standard.