• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.43-53
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• 2003

Unlike in analog display devices, the physical screen resolution in digital devices are fixed from the manufacturing. It is a weak point on digital devices. The screen resolution displayed in digital display devices is varied. Thus, interpolation or decimation of the resolution on the display is needed to make the input pixels equal to the screen resolution., This process is called image scaling. Many researches have been developed to reduce the hardware cost and distortion of the image of image scaling algorithm. In this paper, we proposed a Winscale algorithm. which modifies the scale up/down in continuous domain to the scale up/down in discrete domain. Thus, the algorithm is suitable to digital display devices. Hardware implementation of the image scaler is performed using Verilog XL and chip is fabricated in a 0.5${\mu}{\textrm}{m}$ Samsung SOG technology. The hardware costs as well as the scalabilities are compared with the conventional image scaling algorithms that are used in other software. This Winscale algorithm is proved more scalable than other image-scaling algorithm, which has similar H/W cost. This image-scaling algorithm can be used in various digital display devices that need image scaling process.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

• Journal of radiological science and technology
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• v.35 no.4
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• pp.299-308
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• 2012

To perform patient dose surveys in major interventional radiography procedures as a mean of inter-institutional comparison and of establishing reference dose levels with the ultimate goal of optimizing patient doses in the field of interventional radiography. We reviewed international patient dose survey data in the literature and measured patient dose in major interventional radiography procedures (TACE, AVF, PTBD, TFCA, GDC embolization). ESD(Entrance Skin Dose) was measured using TLD chips attached to the patient skin and ED(Effective Dose) was calculated using angiography unit-derived DAP. A survey of patient dose in interventional radiography procedures were also performed with a questionnaire for interventional radiologists and we proposed a guideline for optimizing patient doses in the field of interventional radiology. The patient dose survey data in interventional radiography procedures were very rare in literature compared with those in diagnostic radiography procedures. In TACE, the mean ED was 25.43 mSv and the mean ESD was 511.75 mGy. The mean ED of TACE was not high, but the cumulative dose should be checked, due to longer procedure TACE. In TFCA, the mean ED was 22.6 mSv and it was relatively high compared with data of other countries. In GDC embolization, the mean ED was not available, because GDC embolization was performed with old Image-Intensifier-type unit and there has no unit-installed ionization chamber. Also, the mean ESD of GDC embolization was up to 2,264 mGy and further studies are needed to calculate the net ED of GDC embolization. Patient dose occurred during interventional radiography procedures are high related with the difficulty of the procedure, fluoroscopy time, the number of angiographies and the treatment protocol. Therefore, continuous education and efforts should be made to optimize the patient dose in the field of interventional radiology.