• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.18 no.1
• /
• pp.116-121
• /
• 2009

Thermosonic flip chip bonding is an important technology for the electronic packaging due to its simplicity, cost effectiveness and clean and dry process. Mechanical properties of the horn and the shank, such as the natural frequency and the amplitude, have a great effect on the bonding capability of the transverse flip chip bonding system. In this research, two kinds of study are performed. The first is the new design of the clamp and the second is the effect of tolerance parameters to the performance of the system. The clamp with a bent shape is newly designed to hold the nodal point of the flip chip. The second is the effect of the design parameters on the vibration amplitude and planarity at the end of the shank. The variation of the tolerance parameters changes the amplitude and the frequency of the vibration of the shank. They, in turn, have an effect on the quantity of the plastic deformation of the gold ball bump, which determined the quality of the flip chip bonding. The tolerance parameters that give the great effect on the amplitude of the shank are determined using Taguchi's method. Error of set-up angle, the length and diameter of horn and error of the length of the shank are determined to be the parameters that have peat effect on the amplitude of the system.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.4
• /
• pp.286-292
• /
• 2004

In this paper we present a static performance estimation technique of on-chip bus architectures. The proposed technique requires the static scheduling of function blocks of a task to analyze bus conflicts caused by simultaneous accesses from processing elements to which function blocks are mapped. To apply it to multitask applications, the concurrent execution of the function blocks of different tasks also should be considered. Since tasks are scheduled independently, considering all cases of concurrency in each processing element is impractical. Therefore we make an average estimate on the effects of other tasks with respect to bus request rate and bus access time. The proposed technique was incorporated with our exploration framework for on-chip bus architectures, Its viability and efficiency are validated by a preliminary example.

• Journal of the Microelectronics and Packaging Society
• /
• v.17 no.4
• /
• pp.1-9
• /
• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• Journal of Sensor Science and Technology
• /
• v.15 no.2
• /
• pp.112-119
• /
• 2006

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.4 s.37
• /
• pp.315-321
• /
• 2005

Chip-on-glass technology to attach IC chip directly on the glass substrate of flat panel display was studied by using induction heating body in AC magnetic field. With applying magnetic field of 230 Oe at 14 kHz, the temperature of an induction heating body made with Cu electrodeposited film of 5 mm${\times}$5 mm size and $600{\mu}m$ thickness reached to $250^{\circ}C$ within 60 seconds. However, the temperature of the glass substrate was maintained below $100^{\circ}C$ at a distance larger than 2 mm from the Cu induction heating body. COG bonding was successfully accomplished with reflow of Sn-3.5Ag solder bumps by applying magnetic field of 230 Oe at 14 kHz for 120 seconds to a Cu induction heating body of 5mm${\times}$5mm size and $600{\mu}m$ thickness.

• Design & Manufacturing
• /
• v.6 no.2
• /
• pp.74-78
• /
• 2012

A multi-cavity injection mold system of protein chip for point-of-care with cavity temperature and pressure sensors was proposed in this work. In advance of manufacturing for the multi-cavity injection mold system, a single cavity injection mold system to mold protein chip was considered. Injection molding analysis for the presented system was performed to optimize the process of the molding and suggest guides to design. On the basis of the results for the single cavity system, a multi-cavity injection mold system for protein chip was analyzed, designed and manufactured with cavity temperature and pressure sensors. Results of balanced filling for protein chip models were obtained from the presented mold system.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.11 no.5
• /
• pp.45-52
• /
• 2002

In an end milling process, the undeformed chip section area and cutting forces vary periodically with the phase change of the tool. However, the real undeformed chip section area deviates from the geometrically ideal one owing to the cutter runout and tool shape error. In the current study, a method of estimating the real undeformed chip section area which reflects the cutter runout and tool shape error is presented during up-end milling processes of Inconel 718. The specific cutting forces, $K_r$ and $K_t$ are defined as the radial and tangential cutting forces divided by the modified chip section area, respectively. Both of the $K_{r}$ and $K_t$ values become smaller as the helix angle increases from $30^{\circ}$ to $40^{\circ}$. Whereas they become larger as the helix angle increases from $40^{\circ}$ to $50^{\circ}$. The $K_r$ and $K_t$ values show a tendency to decrease with increase of the modified chip section area.a.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.13 no.3
• /
• pp.301-307
• /
• 2002

A multilayer ceramic chip antenna with helical structure is analyzed to enhance the narrow bandwidth of conventional ceramic chip antennas. The simulations are performed by HFSS to verify the effects of structural parameters on impedance bandwidth. The multilayer ceramic chip antennas consist of a rectangular-parallelepiped ceramic body$({\varepsilon}_r=7.8,\; tan\; {\delta}=0.0043)$ and helical conductor patterns are embedded in the ceramic body using LTCC-MLC technology. 3D structure design of the multilayer ceramic chip antenna suitable for IMT-2000 (1,920~2,170 MHz) handset has been implemented, and experimental results are presented and discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.319-320
• /
• 2006

In order to improve the ESD(Electrical Static Discharge) resistance of multilayer chip varistors, we have investigated ZnO-$Pr_6O_{11}$ based chip varistor by applying tape casting technology, whose fundamental component were ZnO : $Pr_6O_{11}$ :$Co_3O_4$: $Y_2O_3$: $Al_2O_3$=93.67: 2.53:2.53:1.25 : 0.015 (wt %). The effect of sintering condition on the multilayer chip varistors and electric properties was studied. The electrical properties and ESD resistance of multilayer chip varistor could be influenced the sintering temperature and condition.

• ETRI Journal
• /
• v.22 no.4
• /
• pp.13-24
• /
• 2000

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multi-processor designs.