• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.3-3
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• 1995

Plastic IC encapsulation utilizing lead on chip(LOC) die attach technique allows higher device density per unit package area, and faster current speed and easter leadframe design. Nevertheless, since the top surface of the chip is directly attached to the area of the leadframe with a double-sided adhesive tape in the LOC package, it tends to be easily damaged by the leadframe, leading to limitation in its utilization. In this work, it is detailed how the damage of the chip surface occurs, and it is influenced and improved by the LOC construct.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.41-48
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• 2010

To improve the pot life of one-part in-house anisotropic conductive paste (ACP) formulations, 2-methyl imidazole curing accelerator powders were encapsulated with five agents. Through measuring the melting point of the five agents using DSC, it was confirmed that a encapsulation process with liquid-state agents is possible. Viscosity of ACP formulations containing the encapsulated imidazole powders was measured as a function of storage time from viscosity measurements. As a result, pot life of the formulations containing imidazole powders encapsulated with stearic acid and carnauba wax was improved, and these formulations indicated similar curing behaviors to a basic formulation containing rare imidazole. However, the bondlines made of these formulations exhibited low average shear strength values of about 37% level in comparison with the basic formulation.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.2
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• pp.102-110
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• 2001

In this paper, methods to analyze wire sweep and paddle shift during the semiconductor ship-encapsulation process have been studied. The analysis of wire sweep includes flow-field analysis in a complicated geometry, drag-force calculation for given flow of fluid, and wire-deformation calculation for given loads. The paddle-shift analysis is used to analyze the deformation of the paddle due to the pressure difference in two cavities. the analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The numerical solution is used for more accurate calculation of wire-sweep. The numerical results of wire sweep show good agreements with the experimental ones.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.2
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• pp.10-18
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• 2011

In order to develop highly-integrated RGBY(Red, Green, Blue, Yellow) LED light, a high thermal radiation ceramic package was manufactured, and the encapsulation process was applied with a vacuum printing encapsulation system(VPES). After the completion of vacuum printing, the shape of the encapsulation layer could be controlled by heat treatment during the curing process, and the optical power became highly increased as the encapsulation layer approached a dome shape. The optical characteristics involved in a Correlated Color Temperature(CCT), a Color Rendering Index (CRI), and the efficiency of RGBY LED light were able to be identified by the experimental designing method. Regarding the characteristics of the white light of RGBY LED light, which were measured on the basis of the aforementioned optical characteristics, CRI posted 88, CCT recorded 5,720[$^{\circ}K$], and efficiency exhibited 52[lm/W]. The chip temperature of RGBY LEDs was below 55[$^{\circ}C$] when the consumption power of LED chips was 0.1[W] for the red, 0.3[W] for the green, 0.08[W] for the blue, and 0.24[W] for the yellow. Also, the thermal resistance of the highly-integrated RGBY LED light measured by T3Ster was 2.3[K/W].

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.10
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• pp.849-856
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• 2012

Chip on board type white light emitting diode on metal core printed circuit board with high thixotropy silicone is fabricated by vacuum printing encapsulation system. Encapsulant is chosen by taking into account experimental results from differential scanning calorimeter, shearing strength, and optical transmittance. We have observed that radiant flux and package efficacy are increased from 336 mW to 450 mW and from 11.9 lm/W to 36.2 lm/W as single dome diameter is varied from 2.2 mm to 2.8 mm, respectively. Double encapsulation structure with 2.8 mm of dome diameter shows further significant enhancement of radiant flux and package efficacy to 667 mW and 52.4 lm/W, which are 417 mW and 34.8 lm/W at single encapsulation structure, respectively.

• Journal of Mechanical Science and Technology
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• v.14 no.2
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• pp.251-258
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• 2000

Thermal deformation in an electronic package due to thermal strain mismatch is investigated. The warpage and the in-plane deformation of the package after encapsulation is analyzed using the laminated plate theory. An exact solution for the thermal deformation of an electronic package with circular shape is derived. Theoretical results are presented on the effects of the layer geometries and material properties on the thermal deformation. Several applications of the exact solution to electronic packaging product development are illustrated. The applications include lead on chip package, encapsulated chip on board and chip on substrate.

• Journal of the Korean Society of Radiology
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• v.8 no.7
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• pp.371-376
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• 2014

The process of flip-chip bump bonding, Au wire bonding and encapsulation were sucessfully developed and modularized. The CdTe sensor and ROIC were optimally jointed together at $150^{\circ}C$ and $270^{\circ}C$ respectively under24.5 N for 30s. To make SnAg bump on ROIC easy to be bonded, the higher bonding temperature was established than CdTe sensor's. In addition, the bonding pressure was lowered minimally because CdTe Sensor is easier to break than Si Sensor. CdTe multi-energy sensor module observed were no electrical failures in the joints using developed flip chip bump bonding and Au wire bonding process. As a result of measurement, shearing force was $2.45kgf/mm^2$ and, it is enough bonding force against threshold force, $2kgf/mm^2s$.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.1-10
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• 2020

This paper reviews the recent development of electronic textile technology, mainly focusing on chip-textile bonding. Before the chip-textile bonding, a circuit on the textile should be prepared to supply the electrical power and signal to the chip mounted on the fabrics. Either embroidery with conductive yarn or screen-printing with the conductive paste can be applied to implement the circuit on the fabrics depending on the circuit density and resolution. Next, chip-textile bonding can be performed. There are two choices for chip-textile bonding: fixed connection methods such as soldering, ACF/NCA, embroidery, crimping, and secondly removable connection methods like a hook, magnet, zipper. Following the chip-textile bonding process, the chip on the textile is generally encapsulated using PDMS to ensure reliability like water-proof.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)