• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.803-813
• /
• 2020

This paper presents a high efficiency resonant flyback converter using a single-chip microcontroller. The proposed converter primary performs the resonant switching by applying the asymmetrical pulse-width modulation (APWM) to the half-bridge power topology. And the converter secondary uses the diode flyback rectifier as its power topology and operates with the zero current switching (ZCS). Thus the proposed converter achieves high efficiency. The total structure of proposed converter is very simple because it uses a single-chip microcontroller and bootstrap circuit for its control and drive, respectively. First, this paper describes the converter operation according to each operation mode and shows its steady-state analysis. And the software control algorithm and drive circuits operating the proposed converter are explained. Then, the operation characteristics of proposed converter are shown through the experimental results of an implemented prototype based on each explanation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.40 no.7
• /
• pp.1347-1353
• /
• 2015

We implemented a 10 Gb/s 4-channel vertical cavity surface emission lasers (VCSEL) driver array in a $0.13{\mu}m$ CMOS process technology. To enhance high current resolution, power dissipation, and chip space area, digital APC/AMC with time division sensing technology is primarily adopted. The measured -3 dB frequency bandwidth is 9.2 GHz; the small signal gain is 10.5 dB; the current resolution is 0.01 mA/step, suitable for the wavelength operation up to 10 Gb/s over a wide temperature range. The proposed APC and AMC demonstrate 5 to 20 mA of bias current control and 5 to 20 mA of modulation current control. The whole chip consumes 371 mW of low power under the maximum modulation and bias currents. The active chip size is $3.71{\times}1.3mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.6B
• /
• pp.456-468
• /
• 2008

In this paper, we design Input/Output modules as a preference work for implementation of hybrid two stage AWG based WDM-PON and verify operations of each function modules through the logic simulation. This WDM-PON system provides service to 128 ONUs through 32 wavelength and one wavelength is shared for upstream transmission with four ONU while each wavelength is allocated to each ONU for downstream transmission. The designed WDM-PON MAC chip is based on sub-MAC which consists of one control unit and reception unit and four transmission unit. To design the reception and transmission unit of sub-MAC, we define the functions of the sub-MAC, pins of the modules, control signal and timing of each signal. We intend to design MAC chip with 1Gbps transmission rate. Thus the designed MAC chip is worked on 125MHz clock rate. We define FSM and design Input/Output modules with VHDL. The logic simulation of the modules is executed by the ModelSIM simulator.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.10 no.2
• /
• pp.176-183
• /
• 2017

There is a problem of long erase and program times in testing large-density memories. Also, there is a need of testing the VT voltages of EEPROM cells at each step during the reliability test. In this paper, a cell verification module is designed for a 512kb EEPROM and a CG (control gate) driver is proposed for measuring the VT voltages of a split gate EEPROM having negative erase VT voltages. In the proposed cell verification module, asymmetric isolated HV (high-voltage) NMOS devices are used to apply negative voltages of -3V to 0V in measuring erase VT voltages. Since erasing and programming can be done in units of even pages, odd pages, or a chip in the test time reduction mode, test time can be reduced to 2ms in testing the chip from 4ms in testing the even and the odd pages.

• Journal of IKEEE
• /
• v.25 no.3
• /
• pp.517-527
• /
• 2021

This paper presents the phase-shift full-bridge DC-DC converter using the one-chip micom. The proposed converter primary is the full-bridge power topology that operates with the unipolar pulse-width modulation (PWM) by the phase-shift method, and the secondary is the full-bridge full-wave rectifier composed of four diodes. The control of proposed converter is performed by the one-chip micom and its MOSFET switches are driven by the bootstrap circuit. Thus the total system of proposed converter is simple. The proposed converter achieves high-efficiency using the resonant circuit and blocking capacitor. In this paper, first, the power-circuit operation of proposed converter is explained according to each operation mode. And the power-circuit design method of proposed converter is shown, and the software control algorithm on the micom and the feedback and switch drive circuits operating the proposed converter are described, briefly. Then, the operation characteristics of proposed converter are validated through the experimental results of a designed and implemented prototype converter by the shown design and implementation method in this paper. The highest efficiency in the results was about 92%.

• The Journal of the Acoustical Society of Korea
• /
• v.25 no.2
• /
• pp.61-71
• /
• 2006

An MP3 encoder chip has been designed and fabricated with the hardware and software co-design concepts. In the aspect of the software. the calculation cycles of the distortion control loop. which requires most of the calculation cycles in MP3 encoding procedure. have been reduced to $67\%$ of the original algorithm through the 'scale factor Pre-calculation'. By using a floating Point 32 bit DSP core and designing the FFT block with the hardware. we can get the additional reduction of the calculation cycles in addition to the software optimization. The designed chip has been verified using HW emulation and fabricated via 0.25um CMOS technology The fabricated chip has the size of $6.2{\time}6.2mm^2$ and operates normally on the test board in the qualitative and quantitative aspect.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10b
• /
• pp.1257-1260
• /
• 1996

This paper describes a fully digitalized driver for BLDC motors and the driver is realized by a single chip microprocessor. The speed change can be done by using the signal obtained from the position detecting sensor and adjusting the pulse width at the input channel of power module. In order to verify the effectiveness, an repetitive control method is adopted in the speed control tracking a periodic reference change in the BLDC motor system. The experimental results are shown for the reference tracking accurately according to the design parameter variation in the repetitive controller design.

• Proceedings of the IEEK Conference
• /
• 2004.08c
• /
• pp.836-841
• /
• 2004

This paper describes ASIC design for brightness revision control, A LED Pixel Matrix (LPM) design and LPM in natural color LED vision. A designed chip has 256 levels of gradation correspond to each Red, Green, Blue LED pixel respectively, which have received 8bit image data. In order to maintain color uniformity by reducing the original rank error of LED, we adjusted the specific character value 'a' and brightness revision value 'b' to pixel unit, module unit and LED vision respectively by brightness characteristic function with 'Y=aX+b'. In this paper, if designed custom chip and brightness revision control method are applied to manufacturing of natural color LED vision, we can obtain good quality of image. Furthermore, it may decrease the cost for manufacturing LED vision or installing the plants.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.221-225
• /
• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.909-912
• /
• 2005

According to miniaturization trend of rehabilitation medical equipment such as hearing aid, study to replace previous complex system with semiconductor SOC (System-on-Chip) chip becomes lively. In this study, after investigating of existent hearing aid performance in circuit design approach, low electric power consuming, single power supply (1.4V battery) CMOSS OP AMP was designed. Analog circuit design tools such as Hspice and Cadence were used for circuit simulation and implementing layout design. This study shows technical methods particularly for layout design. The work is done in pmos and nmos active element layout design in addition to passive element design such as resister, capacitor and inductor.