• Journal of Platform Technology
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• v.8 no.1
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• pp.24-32
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• 2020

This paper designed and manufactured a chip mounter based on 3D printer technology that can be used for educational research or sample production to disseminate chip mounter, a core technology of SMT line. A stepper motor with open loop control is used for low cost drive design. The shortcomings of the motor's vibration and disassembly caused by the use of the step motor were compensated by the Micro-Step control method. In the chip mounter experiment, the gerber file was generated on the small chip mounter, printed at the actual size, and the solder cream was printed on the HASL-treated PCB in the same manner as the sample board fabrication. As a result of the experiment, unlike the 2012 micro components, parts such as SOIC and TQFP that require correction are twice as long as the component mounting time, but it can be confirmed that they are mounted relatively accurately. In addition, as a result of repeatedly measuring the error of the initial position 10 times, it was confirmed that a relatively small error of about 0.110mm occurs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.459-461
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• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.984-995
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• 1996

Data errors according to the various noises caused in the satellite communication links are corrected by the Viterbi decoding algorithm which has extreme error correcting capability. In this paper, we designed and implemented a convolutional encoder and Viterbi decoder ASIC which is used to encode the input data at the transmit side and correct the errors of the received data at the receive side for use in the VSAT communication system. And this chip may be used in any BPSK, QPSK, or OQPSK transmission system. The ambiguity resolver corrects PSK modem ambiguities by delaying, interting, and/or exchanging code symbol to restore their original sequence and polarity. In case of previous decoding system, ambiguity state(AS) of data is resolved by external control logic and extra redundancy data are needed to resolve AS. But, by adopting decoder proposed in this paper, As of data is resolved automatically by internal logic of decoder in case of continuous mode, and by external As line withoug extra redudancy data in burst mode case. So, decoding parts are simple in continuous mode and transmission efficiency is increased in bust mode. The features of this chip are full duplex operation with independent transmit and receive control and clocks, start/stop inputs for use in burst mode systems, loopback function to verify encoder and decoder, and internal or external control to resolve ambinguity state. For verification of the function and performance of a fabricated ASIC chip, we equiped this chip in the Central and Remote Earth Station of VSAT system, and did the performance test using the commerical INTELSAT VII under the real satellite link environmens. The results of test were demonstrated the superiority of performance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1671-1674
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• 2014

This paper presents a frequency-dependent cell impedance analysis chip for use in cancer and normal cell discrimination. The previous cell impedance analysis chips for flowing cells cannot allow enough time for cell-to-electrode contact to monitor frequency-dependent impedance response. Another type of the previous cell impedance analysis chips for the cells clamped by membranes need complex sample control for making stable cell-to-electrode contact. We present a new impedance analysis chip using the microchamber array, on which a PDMS cover is placed to make stable cell-to-electrode contact for the individual cell trapped in each microchamber; thus achieving frequency-dependent single-cell impedance analysis without complex sample control. Compared to the normal cells, the magnitude of NHBE cells is $60.07{\sim}97.41k{\Omega}$ higher than A549 cells in the frequency range of 95.6 kHz~2MHz and the phase of NHBE is $3.96^{\circ}{\sim}20.8^{\circ}$ higher than A549 cells in the frequency range of 4.37 kHz~2MHz, respectively. It is demonstrated experimentally that the impedance analysis chip performs frequency-dependent cell impedance analysis by making stable cell-to-electrode contact with simple sample control; thereby applicable to the normal cell and cancer cell discrimination.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.2 s.245
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• pp.110-116
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• 2006

A syringe pump or a device using high electric voltage has been used for controlling flows inside a LOC (lab-on-a-chip). Compared to LOC, however, these microfluidic devices are large and heavy that they are burdensome for a portable ${\mu}-TAS$ (micro total analysis system). In this study, a new flow control technique employing pressure regulators and pressure chambers was developed. This technique utilizes compressed air to control the micro-scale flow inside a LOC, instead of a mechanical actuator or an electric power supply. The pressure regulator controls the output air pressure by adjusting the variable resistor attached. We checked the feasibility of this system by measuring the flow rate inside a capillary tube of $100{\mu}m$ diameter in the Re numbers ranged from 0.5 to 50. In addition, the performance of this flow control system was compared with that of a conventional syringe pump. The developed flow control system was found to show superior performance, compared with the syringe pump. It maintains automatically the: air pressure inside a pressure chamber whether the flow inside the capillary tube is on or off. Since the flow rate is nearly proportional to the resistance, we can control flow in multiple microchannels precisely. However, the syringe pump shows large variation of flow rate when the fluid flow is blocked in the microchannel.

• Korean Journal of Materials Research
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• v.29 no.2
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• pp.106-115
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• 2019

Recently, metal cases are widely used in smart phones for their luxurious color and texture. However, when a metal case is used, electric shock may occur during charging. Chip capacitors of various values are used to prevent the electric shock. However, chip capacitors are vulnerable to electrostatic discharge(ESD) generated by the human body, which often causes insulation breakdown during use. This breakdown can be eliminated with a high-voltage chip varistor over 340V, but when the varistor voltage is high, the capacitance is limited to about 2pF. If a chip capacitor with a high dielectric constant and a chip varistor with a high voltage can be combined, it is possible to obtain a new device capable of coping with electric shock and ESD with various capacitive values. Usually, varistors and capacitors differ in composition, which causes different shrinkage during co-firing, and therefore camber, internal crack, delamination and separation may occur after sintering. In addition, varistor characteristics may not be realized due to the diffusion of unwanted elements into the varistor during firing. Various elements are added to control shrinkage. In addition, a buffer layer is inserted in the middle of the varistor-capacitor junction to prevent diffusion during firing, thereby developing a co-fired product with desirable characteristics.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.360-365
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• 2003

In this paper, we have developed a general purpose motion controller using an FPGA(Field Programmable Gate Array). The multi-PID controllers on a single chip are implemented as a system-on-chip for multi-axis motion control. We also develop a PC GUI for an efficient interface control. Comparing with the commercial motion controller LM 629 it has multi-independent PID controllers so that it has several advantages such as space effectiveness, low cost and lower power consumption. In order to test the performance of the proposed controller, robot finger is controlled. The robot finger has three fingers with 2 joints each. Finger movements show that position tracking was very effective. Another experiment of balancing an inverted pendulum on a cart has been conducted to show the generality of the proposed FPGA PID controller. The controller has well maintained the balance of the pendulum.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.647-649
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• 2004

When a controller is implemented by a one-chip processor with fixed-point operations, the finite alphabet problem usually occurs since parameters and signals should be taken in a finite set of values. This paper formulates PID finite alphabet PID control problem which combines the PID controller with the finite alphabet problem. We will propose a PID parameter tuning method based on an optimization algorithm under the finite alphabet condition. The PID parameters can be represented by a fixed-point representation, and then the problem is formulated as an optimization with constraints that parameters are taken in the finite set. Some simulation are to be performed to exemplify the performance of the PID parameter tuning method proposed in this paper.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1133-1136
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• 1998

The optimization theory in this paper was down a power consumption and a chip area that this paper use a low number of transistor and compare two circuits of the input-output control. the first, design a circuit of pipeline Multiplexor in sequence of invert. the second, operated a control of N numbers of MUX using a decoder. compare a number of transistor, a chip area in semiconductor and a power consumption of two circuit.