• 제목/요약/키워드: Chemical-mechanical polishing

검색결과 499건 처리시간 0.031초

구리 CMP 슬러리를 위한 산화제 $H_2O_2$의 안정성 (Stability of Oxidizer $H_2O_2$ for Copper CMP Slurry)

  • 이도원;김인표;김남훈;김상용;서용진;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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    • pp.382-385
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    • 2003
  • Chemical mechanical polishing(CMP) is an essential process in the production of copper-based chips. On this work, the stability of Hydrogen Peroxide($H_2O_2$) as oxidizer of Cu CMP slurry has been investigated. $H_2O_2$ is known as the most common oxidizer in Cu CMP slurry. Copper slowly dissolves in $H_2O_2$ solutions and the interaction of $H_2O_2$ with copper surface had been studied in the literature. Because hydrogen peroxide is a weak acid in aqueous solutions, a passivation-type slurry chemistry could be achieved only with pH buffered solution.[1] Moreover, $H_2O_2$ is so unstable that its stabilization is needed using as oxidizer. As adding KOH as pH buffering agent, stability of $H_2O_2$ decreased. However, stability went up with putting in small amount of BTA as film forming agent. There was no difference of $H_2O_2$ stability between KOH and TMAH at same pH. On the other hand, $H_2O_2$ dispersion of TMAH is lower than that of KOH. Furthermore, adding $H_2O_2$ in slurry in advance of bead milling lead to better stability than adding after bead milling. Generally, various solutions of phosphoric acids result in a higher stability. Using Alumina C as abrasive was good at stabilizing for $H_2O_2$; moreover, better stability was gotten by adding $H_3PO_4$.

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STI CMP후 Topology에 따른 Gate Etch, Transistor 특성 변화 (Property variation of transistor in Gate Etch Process versus topology of STI CMP)

  • 김상용;정헌상;박민우;김창일;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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    • pp.181-184
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    • 2001
  • Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

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$BaTiO_3$$TiO_2$ 연마제 첨가를 통한 BTO박막의 CMP (CMP of BTO Thin Films using $TiO_2$ and $BaTiO_3$ Mixed Abrasive slurry)

  • 서용진;고필주;김남훈;이우선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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    • pp.68-69
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    • 2005
  • BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant. It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the self-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS), respectively. The removal rate of BTO thin film using the$ BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%. The sufficient within-wafer non-uniformity (WIWNU%)below 5% was obtained in each abrasive at all concentrations. The surface morphology of polished BTO thin film was investigated by atomic force microscopy (AFM).

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단결정 SOI트랜스듀서 및 회로를 위한 Si직접접합 (Silicon-Wafer Direct Bonding for Single-Crystal Silicon-on-Insulator Transducers and Circuits)

  • 정귀상
    • 센서학회지
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    • 제1권2호
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    • pp.131-145
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    • 1992
  • 본 논문은 SOI트랜스듀서 및 회로를 위해, Si 직접접합과 M-C국부연마법에 의한 박막SOI구조의 형성 공정을 기술한다. 또한, 이러한 박막SOI의 전기적 및 압저항효과 특성들을 SOI MOSFET와 cantilever빔으로 각각 조사했으며, bulk Si에 상당한다는 것이 확인되었다. 한편, SOI구조를 이용한 두 종류의 압력트랜스듀서를 제작 및 평가했다. SOI구조의 절연층을 압저항의 유전체분리층으로 이용한 압력트랜스듀서의 경우, $-20^{\circ}C$에서 $350^{\circ}C$의 온도범위에 있어서 감도 및 offset전압의 변화는 자각 -0.2% 및 +0.15%이하였다. 한편, 절연층을 etch-stop막으로 이용한 압력트랜스듀서에 있어서의 감도변화를 ${\pm}2.3%$의 표준편차 이내로 제어할 수 있다. 이러한 결과들로부터 개발된 SDB공정으로 제작된 SOI구조는 집적화마이크로트랜스듀서 및 회로개발에 많은 장점을 제공할 것이다.

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연마제 첨가를 통한 BTO Film의 CMP (CMP of BTO Thin Films using Mixed Abrasive slurry)

  • 김병인;이기상;박정기;정창수;강용철;차인수;정판검;신성헌;고필주;이우선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 영호남 합동 학술대회 및 춘계학술대회 논문집 센서 박막 기술교육
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    • pp.101-102
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    • 2006
  • BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant, It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the sell-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS). respectively. The removal rate of BTO thin film using the $BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%.

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Sodium Periodate 기반 Slurry의 pH 변화가 Ru CMP에 미치는 영향 (Effect of pH in Sodium Periodate based Slurry on Ru CMP)

  • 김인권;조병권;박진구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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    • pp.117-117
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    • 2008
  • In MIM capacitor, poly-Si bottom electrode is replaced with metal bottom electrode. Noble metals can be used as bottom electrodes of capacitors because they have high work function and remain conductive in highly oxidizing conditions. In addition, they are chemically very stable. Among novel metals, Ru (ruthenium) has been suggested as an alternative bottom electrode due to its excellent electrical performance, including a low leakage of current and compatibility to high dielectric constant materials. Chemical mechanical planarization (CMP) process has been suggested to planarize and isolate the bottom electrode. Even though there is a great need for development of Ru CMP slurry, few studies have been carried out due to noble properties of Ru against chemicals. In the organic chemistry literature, periodate ion ($IO_4^-$) is a well-known oxidant. It has been reported that sodium periodate ($NaIO_4$) can form $RuO_4$ from hydrated ruthenic oxide ($RuO_2{\cdot}nH_2O$). $NaIO_4$ exist as various species in an aqueous solution as a function of pH. Also, the removal mechanism of Ru depends on solution of pH. In this research, the static etch rate, passivation film thickness and wettability were measured as a function of slurry pH. The electrochemical analysis was investigated as a function of pH. To evaluate the effect of pH on polishing behavior, removal rate was investigated as a function of pH by using patterned and unpatterned wafers.

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산화제 첨가조건이 부동태막의 형성에 미치는 영향 (Chemical Mechanical Polishing Properties of Copper Passive Layer)

  • 한상준;이우선;최권우;박성우;이영균;서용진
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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    • pp.538-538
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    • 2008
  • 금속계열의 박막을 평탄화하기위해서는 슬러리에 함유된 산화제에 의해 부동태층의 형성이 선행되어야 한다. 따라서 본 논문에서는 Copper 박막의 표면을 부동태층으로 형성시키고 CMP공정을 하기위해 산화제에 dipping을 시켰으며 삼화제의 종류는 $H_2O_2$, MSW2000B, $KIO_3$로 하고 dipping 시간은 30초, 60초, 90초, 3분, 10분으로 하여 시간과 산화제 종류에 따른 부동태층의 변화를 연구하였다. 부동태층의 관찰은 FESEM을 이용하여 표면과 단면을 관찰하였고 부동태층의 조성비율은 EDX를 이용하여 조사하였다. MSW 2000B의 경우는 부동태층이 덩어리 모양으로 형성되었으며 포화현상은 3분에 일어났다. 반면에 $H_2O_2$의 경우는 부동태층이 침상 모양으로 형성되었으며 포화현상은 90초에 일어났다. 산화제에 의해 부동태층을 형성시킨 후 POLI-450을 이용하여 평탄화공정을 진행하였으며 CMP공정조건은 부동태층의 연질상태임을 감안하여 헤드 스피드 20rpm, 플레이튼 스피드 10rpm, 슬러리 주입속도 90ml/min, 공정온도는 상온으로 하여 진행하였다. $H_2O_2$를 산화제로 사용하여 dipping을 하고 CMP를 하였을 경우에 균일한 박막을 확보 할 수 있었으며 CMP 공정 후 copper 박막의 균일성은 FESEM을 이용하여 관찰 하였다.

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$MnO_2$ 연마제가 실리카 슬러리에 미치는 영향에 관한 연구 (Influence of Silica slurry by $MnO_2$ abrasive)

  • 이영균;이우선;박성우;최권우;고필주;한상준;박주선;나한용;서용진
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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    • pp.543-543
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    • 2008
  • 반도체 집적회로의 제조 공정 중 CMP 공정이 필수 핵심기술이 되었다. 이처럼 CMP 공정 기술이 다층 배선 구조의 광역 평탄화를 위해서는 매우 효과적이지만 기계적인 연마패드와 화학적인 식각 작용을 하는 슬러리를 이용하여 연마가 진행되므로 공정 결함이 문제시되어 왔다. 그 중에서도, 소모자재의 비용이 CMP 공정비용의 70% 이상을 차지하는 제조단가가 높다는 단점이 있다. 특히 고가의 슬러리가 차지하는 비중이 40% 이상을 넘고 있어, 슬러리 원액의 소모량을 줄이기 위한 연구들이 현재 활발히 연구 중에 있다. 본 논문에서는 새로운 혼합 연마제 슬러리에 대한 CMP 특성을 통해 기존에 상용화된 슬러리의 CMP 특성과 비교 고찰하여 MAS의 우수성을 입증하고, 최적화된 공정기술 연구의 기반으로 활용하고자 실리카 슬러리에 $MnO_2$ 연마제를 혼합하여 연마특성을 비교분석하였고, AFM, EDX, XRD, TEM분석을 통해 그 가능성을 알아보았다.

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STI CMP후 Topology에 따른 Gate Etch, Transistor 특성 변화 (Property variation of transistor in Gate Etch Process versus topology of STI CMP)

  • 김상용;정헌상;박민우;김창일;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집
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    • pp.181-184
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    • 2001
  • Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

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Utilizing Advanced Pad Conditioning and Pad Motion in WCMP

  • Kim, Sang-Yong;Chung, Hun-Sang;Park, Min-Woo;Kim, Chang-Il;Chang, Eui-Goo
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집
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    • pp.171-175
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    • 2001
  • Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics and metal, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter level dielectrics and metal. Especially, defects like (micro-scratch) lead to severe circuit failure, and affects yield. Current conditioning method - bladder type, orbital pad motion - usually provides unsuitable pad profile during ex-situ conditioning near the end of pad life. Since much of the pad wear occurs by the mechanism of bladder tripe conditioning and its orbital motion without rotation, we need to implement new ex-situ conditioner which can prevent abnormal regional force on pad caused by bladder-type and also need to rotate the pad during conditioning. Another important study of ADPC is related to the orbital scratch of which source is assumed as diamond grit dropped from the strip during ex-situ conditioning. Scratch from diamond grit damaged wafer severely so usual1y scraped. Figure 1 shows the typical shape of scratch damaged from diamond. We suspected that intensive forces to the edge area of bladder type stripper accelerated the drop of Diamond grit during conditioning, so new designed Flat stripper was introduced.

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