• Title/Summary/Keyword: Chemical-mechanical polishing

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A New Method for Deep Trench Isolation Using Selective Polycrystalline Silicon Growth (다결정 실리콘의 선택적 성장을 이용한 깊은 트랜치 격리기술)

  • 박찬우;김상훈;현영철;이승윤;심규환;강진영
    • Journal of the Korean Vacuum Society
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    • v.11 no.4
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    • pp.235-239
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    • 2002
  • A new method for deep trench isolation using selective growth of polycrystalline silicon is proposed. In this method, trench filling is performed by forming polysilicon-inner sidewalls within the trench, and then selectively growing them by reduced chemical vapor deposition using $SiH_2C1_2$gas at $1100^{\circ}C$. The surface profiles of filled trenches are determined mainly by the initial depth of inner sidewalls and the total thickness of selective growth. No chemical mechanical polishing(CMP) process is needed in this new method, which makes the process flow simpler and more reliable in comparison with the conventional method using CMP process.

The Study of ILD CMP Using Abrasive Embedded Pad (고정입자 패드를 이용한 층간 절연막 CMP에 관한 연구)

  • 박재홍;김호윤;정해도
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2001.04a
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    • pp.1117-1120
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    • 2001
  • Chemical mechanical planarization(CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Since IBM's official announcement on Copper Dual Damascene(Cu2D) technology, the semiconductor world has been engaged in a Cu2D race. Today, even after~3years of extensive R&D work, the End-of-Line(EOL) yields are still too low to allow the transition of technology to manufacturing. One of the reasons behind this is the myriad of defects associated with Cu technology. Especially, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasive and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using Ce$O_2$ is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

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Effect of Surface Pretreatment on Film Properties Deposited by Electro-/Electroless Deposition in Cu Interconnection (반도체 구리 배선공정에서 표면 전처리가 이후 구리 전해/무전해 전착 박막에 미치는 영향)

  • Lim, Taeho;Kim, Jae Jeong
    • Journal of the Korean Electrochemical Society
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    • v.20 no.1
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    • pp.1-6
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    • 2017
  • This study investigated the effect of surface pretreatment, which removes native Cu oxides on Cu seed layer, on subsequent Cu electro-/electroless deposition in Cu interconnection. The native Cu oxides were removed by using citric acid-based solution frequently used in Cu chemical mechanical polishing process and the selective Cu oxide removal was successfully achieved by controlling the solution composition. The characterization of electro-/electrolessly deposited Cu films after the oxide removal was then performed in terms of film resistivity, surface roughness, etc. It was observed that the lowest film resistivity and surface roughness were obtained from the substrate whose native Cu oxides were selectively removed.

Copper MOCVD using catalytic surfactant : Novel concept

  • Hwang, Eui-Seong;Lee, Jihwa
    • Proceedings of the Korean Vacuum Society Conference
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    • 1999.07a
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    • pp.30-30
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    • 1999
  • 알루미늄에 비해 전기저항이 낮고 electromigration 및 stress-migration에 대한 저항서이 높은 구리는 차세대 반도체 소자의 배선금속 재료로 여겨지고 있다. 최근 Chemical Mechanical Polishing (CMP) 기술의 도래로 구리배선 공정의 채택이 더욱 앞당겨질 전망이다. 한편, 구리 MOCVD를 위해 다양한 전구체화합물이 합성되었고, 근래에는 Cu(I)(hfc)L (L은 Lewis base 형태의 ligand) 형태의 전구체를 이용한 많은 증착 연구를 통하여 순수하고 전기저항이 낮은 구리 박막의 증착이 보고되었다. 구리 MOCVD의 가장 큰 문제점은 증착속도가 150-$^{\circ}C$20$0^{\circ}C$에서 500$\AA$/min 이하로 낮고 또한 증착된 필름 표면이 매우 거칠다는 데 있다. 이러한 단점으로 인해 전기화학적 증착후 CMP를 적용하는 것이 더욱 경제적이라는 견해가 우세해 지고 있다. 본 강연에서는 박막의 증착 속도와 표면 거칠기를 동시에 향사시키기 위해 catalytic surfactant를 이용한 새로운 MOCVD 개념을 도입하고, 구리 MOCVD에서 단원자층으로 흡착된 요오드 원자가 그 역할을 수행할 수 있음을 보이겠다. 또 요오드원자가 표면반응을 어떻게 수정하여 활성화에너지를 낮추는가를 반응메카니즘으로 밝히고 표면 평탄화의 미시적 해석을 제공하고자 한다. Catalytic Surfactant의 개념은 다른 박막 재료의 MOCVD에도 적용될 수 있으며, 나아가 적절한 기판 표면처리를 통하여 epitaxy도 가능할 것으로 본다.

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A Study of the Effects of Pressure Velocity and Fluid Viscosity in Abrasive Machining Process (입자연마가공에서의 압력 속도 및 유체점도의 영향에 대한 고찰)

  • Yang, Woo-Yul;Yang, Ji-Chul;Sung, In-Ha
    • Tribology and Lubricants
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    • v.27 no.1
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    • pp.7-12
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    • 2011
  • Interest in advanced machining process such as AJM(abrasive jet machining) and CMP(chemical-mechanical polishing) using micro/nano-sized abrasives has been on the increasing demand due to wide use of super alloys, composites, semiconductor and ceramics, which are difficult to or cannot be processed by traditional machining methods. In this paper, the effects of pressure, wafer moving velocity and fluid viscosity were investigated by 2-dimensional finite element analysis method considering slurry fluid flow. From the investigation, it could be found that the simulation results quite corresponded well to the Preston's equation that describes pressure/velocity dependency on material removal. The result also revealed that the stress and corresponding material removal induced by the collision of particle may decrease under relatively high wafer moving speed due to the slurry flow resistance. In addition, the increase in slurry fluid viscosity causes the reduction of material removal rate. It should be noted that the viscosity effect can vary with the shape of abrasive particle.

A Study on the Correlation between Temperature and CMP Characteristics (CMP특성과 온도의 상호관계에 관한 연구)

  • Gwon, Dae-Hui;Kim, Hyeong-Jae;Jeong, Hae-Do;Lee, Eung-Suk;Sin, Yeong-Jae
    • Journal of the Korean Society for Precision Engineering
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    • v.19 no.10
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    • pp.156-162
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    • 2002
  • There are many factors affecting the results of CMP (Chemical Mechanical Polishing). Among them, the temperature is related to the removal rate and WIWNU (Within Wafer Non-Uniformity). In other words, the removal rate is proportional to the temperature and the variation of temperature distribution on a pad affects the non-uniformity within a wafer. In the former case, the active chemistry improves the rate of chemical reaction and the removal rate becomes better. But, there are not many advanced studies. In the latter case, a kinematical analysis between work-piece and pad can be obtained. And such result analysed from the mechanical aspect can be directly related to the temperature distribution on a pad affecting WIWNU. Meanwhile, the temperature change affects the quantities of both slurry and pad. The change of a pH value of the slurry chemistry due to a temperature variation affects the surface state of an abrasive particle and hence the agglomeration of abrasives happens above the certain temperature. And the pH alteration also affects the zeta potential of a pad surface and therefore the electrical force between pad and abrasive changes. Such results could affect the removal rate and etc. Moreover, the temperature changes the 1st and 2nd elastic moduli of a pad which are closely related to the removal rate and the WIWNU.

Characteristic of $WO_3$ Thin Film CMP ($WO_3$ Thin Film의 CMP 특성)

  • Ko, Pi-Ju;Lee, Woo-Sun;Choi, Kwon-Woo;Kim, Tae-Wan;Seo, Yong-Jin
    • Proceedings of the KIEE Conference
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    • 2004.07c
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    • pp.1727-1729
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    • 2004
  • Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP precess, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). we investigated the performance of $WO_3$ CMP used silica slurry, ceria slurry, tungsten slurry. In this paper, the effects of addition oxidizer on the $WO_3$ CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity.

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Effect of slurries on the dishing of Shallow Trench Isolation structure during CMP process

  • Lee, Hoon;Lim, Dae-Soon;Lee, Sang-Ick
    • Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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    • 2002.10b
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    • pp.443-444
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    • 2002
  • The uniformity of field oxide is critical to isolation property of device in STI, so the control of field oxide thickness in STI-CMP becomes enormously important. The loss of field oxide in shallow trench isolation comes mainly from dishing and erosion in STI-CMP. In this paper, the effect of slurries on the dishing was investigated with both blanket and patterned wafers were selected to measure the removal rate, selectivity and dishing amount. Dishing was a strong function of pattern spacing and types of slurries. Dishing was significantly decreased with decreasing pattern spacing for both slurries. Significantly lower dishing with ceria based slurry than with silica based slurry were achieved when narrow pattern spacing were used. Possible dishing mechanism with two different slurries were discussed based on the observed experimental results.

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마이크로 블라스터를 이용한 태양전지용 재생웨이퍼에 관한 연구

  • Lee, Yun-Ho;Gong, Dae-Yeong;Jeong, Sang-Hun;Kim, Sang-Won;Kim, Dong-Hyeon;Seo, Chang-Taek;Jo, Chan-Seop;Lee, Jong-Hyeon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.276-276
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    • 2009
  • Solar cells has been studied mainly the high efficiency and lower prices. Using recycling wafer as a way to realize their money in it, there is a way to manufacture a solar cell substrate. How to play the recycling wafer, CMP(Chemical Mechanical Polishing) and remelting process is the complex and the expensive equipment. However, using the Micro-Blaster, the process easier, and cheaper prices. Micro-Blaster confirmed that the remaining amount of material left after the process recycling wafer surface.

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Analysis of Material Removal Rate Profile and Stress Distribution According to Retainer Pressure (CMP에서 리테이너링의 압력에 따른 연마율 프로파일과 응력 분포 해석)

  • Lee, Hyun-Seop;Lee, Sang-Jik;Jeong, Suk-Hoon;An, Joon-Ho;Jeong, Hea-Do
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.482-483
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    • 2009
  • In chemical mechanical planarization (CMP) process, the uniformity of stress acting on wafer surface is a key factor for uniform material removal of thin film especially in the oxide CMP. In this paper, we analyze the stress on the contact region between wafer and pad with finite-element analysis (FEA). The setting pressure acting on wafer back side was $500g/cm^2$ and the retainer pressure was changed from 300 to $700g/cm^2$. The polishing test is also done with the same conditions. The material removal rate profiles well-matched with stress distribution.

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