• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.111-111
• /
• 2008

태양전지는 태양에너지를 직접 전기에너지로 변환시켜주는 광전 소자로서 구조적으로 단순하고 제조 공정도 비교적 간단하지만, 실용화를 위해서는 비용적인 측면이 많은 걸림돌이 되고 있다. 기존의 실리콘 태양전지는 낮은 광흡수율, 고비용임에도 불구하고 가장 많이 활용되고 있는 태양전지 기술이다. 그러나 태양전지의 경제성 향상과 실용화를 위해서는 기존의 실리콘 태양전지 보다 고효율 및 고신뢰도의 박막형 태양전지의 개발이 필요하다. 박막헝 태양전지의 재료로는 비정질 실리콘, 다결정 실리콘. CIGS, CdTe 등이 있다. 그 중에서도 박막형 태양전지에 광흡수층 물질로는 밴드갭 에너지 (l.4eV 부근), 변환 효율, 경제성 등을 고려했을 때 II-VI족 화합물인 CdTe가 가장 적합한 것으로 각광받고 있다. 하지만 아직까지 실리콘 태양전지에 비해 효율이 많이 떨어지는 단점을 가지고 있기 때문에 효율을 더 끌어올리기 위한 연구가 활발히 진행되고 있는 실정이다. 또한 CMP(chemical mechanical polishing) 공정은 반도체 박막 분야뿐만 아니라 물리, 화학 반응의 기초 연구에도 널리 응용이 되는 기술로써, 시료와 연마 패드 사이의 회전마찰에 의한 기계적 연마와 연마제 (abrasive) 에 의한 화학적 에칭으로 박막 표면을 평탄화하는 기술이다. 본 연구에서는 sputtering 법에 의해 증착된 CdTe 박막에 CMP 공정을 적용하여 표면 특성을 개선한 뒤 태양전지 변환 효율과 직접적인 연관성을 가지고 있는 표면 및 광특성의 변화를 CMP 공정 전과 후로 비교하였다. 표면의 변화를 관찰하기 위해서 AFM(atomic forced microscope) 과 SEM(scanning electron microscopy) 을 이용하였으며, 광특성의 비교를 위해서 흡수율과 PL특성을 측정하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07a
• /
• pp.382-385
• /
• 2003

Chemical mechanical polishing(CMP) is an essential process in the production of copper-based chips. On this work, the stability of Hydrogen Peroxide($H_2O_2$) as oxidizer of Cu CMP slurry has been investigated. $H_2O_2$ is known as the most common oxidizer in Cu CMP slurry. Copper slowly dissolves in $H_2O_2$ solutions and the interaction of $H_2O_2$ with copper surface had been studied in the literature. Because hydrogen peroxide is a weak acid in aqueous solutions, a passivation-type slurry chemistry could be achieved only with pH buffered solution.[1] Moreover, $H_2O_2$ is so unstable that its stabilization is needed using as oxidizer. As adding KOH as pH buffering agent, stability of $H_2O_2$ decreased. However, stability went up with putting in small amount of BTA as film forming agent. There was no difference of $H_2O_2$ stability between KOH and TMAH at same pH. On the other hand, $H_2O_2$ dispersion of TMAH is lower than that of KOH. Furthermore, adding $H_2O_2$ in slurry in advance of bead milling lead to better stability than adding after bead milling. Generally, various solutions of phosphoric acids result in a higher stability. Using Alumina C as abrasive was good at stabilizing for $H_2O_2$; moreover, better stability was gotten by adding $H_3PO_4$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11b
• /
• pp.181-184
• /
• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.11a
• /
• pp.68-69
• /
• 2005

BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant. It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the self-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS), respectively. The removal rate of BTO thin film using the$ BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%. The sufficient within-wafer non-uniformity (WIWNU%)below 5% was obtained in each abrasive at all concentrations. The surface morphology of polished BTO thin film was investigated by atomic force microscopy (AFM).

• Journal of Sensor Science and Technology
• /
• v.1 no.2
• /
• pp.131-145
• /
• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.05a
• /
• pp.101-102
• /
• 2006

BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant, It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the sell-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS). respectively. The removal rate of BTO thin film using the $BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.117-117
• /
• 2008

In MIM capacitor, poly-Si bottom electrode is replaced with metal bottom electrode. Noble metals can be used as bottom electrodes of capacitors because they have high work function and remain conductive in highly oxidizing conditions. In addition, they are chemically very stable. Among novel metals, Ru (ruthenium) has been suggested as an alternative bottom electrode due to its excellent electrical performance, including a low leakage of current and compatibility to high dielectric constant materials. Chemical mechanical planarization (CMP) process has been suggested to planarize and isolate the bottom electrode. Even though there is a great need for development of Ru CMP slurry, few studies have been carried out due to noble properties of Ru against chemicals. In the organic chemistry literature, periodate ion ($IO_4^-$) is a well-known oxidant. It has been reported that sodium periodate ($NaIO_4$) can form $RuO_4$ from hydrated ruthenic oxide ($RuO_2{\cdot}nH_2O$). $NaIO_4$ exist as various species in an aqueous solution as a function of pH. Also, the removal mechanism of Ru depends on solution of pH. In this research, the static etch rate, passivation film thickness and wettability were measured as a function of slurry pH. The electrochemical analysis was investigated as a function of pH. To evaluate the effect of pH on polishing behavior, removal rate was investigated as a function of pH by using patterned and unpatterned wafers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.538-538
• /
• 2008

금속계열의 박막을 평탄화하기위해서는 슬러리에 함유된 산화제에 의해 부동태층의 형성이 선행되어야 한다. 따라서 본 논문에서는 Copper 박막의 표면을 부동태층으로 형성시키고 CMP공정을 하기위해 산화제에 dipping을 시켰으며 삼화제의 종류는 $H_2O_2$, MSW2000B, $KIO_3$로 하고 dipping 시간은 30초, 60초, 90초, 3분, 10분으로 하여 시간과 산화제 종류에 따른 부동태층의 변화를 연구하였다. 부동태층의 관찰은 FESEM을 이용하여 표면과 단면을 관찰하였고 부동태층의 조성비율은 EDX를 이용하여 조사하였다. MSW 2000B의 경우는 부동태층이 덩어리 모양으로 형성되었으며 포화현상은 3분에 일어났다. 반면에 $H_2O_2$의 경우는 부동태층이 침상 모양으로 형성되었으며 포화현상은 90초에 일어났다. 산화제에 의해 부동태층을 형성시킨 후 POLI-450을 이용하여 평탄화공정을 진행하였으며 CMP공정조건은 부동태층의 연질상태임을 감안하여 헤드 스피드 20rpm, 플레이튼 스피드 10rpm, 슬러리 주입속도 90ml/min, 공정온도는 상온으로 하여 진행하였다. $H_2O_2$를 산화제로 사용하여 dipping을 하고 CMP를 하였을 경우에 균일한 박막을 확보 할 수 있었으며 CMP 공정 후 copper 박막의 균일성은 FESEM을 이용하여 관찰 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.543-543
• /
• 2008

반도체 집적회로의 제조 공정 중 CMP 공정이 필수 핵심기술이 되었다. 이처럼 CMP 공정 기술이 다층 배선 구조의 광역 평탄화를 위해서는 매우 효과적이지만 기계적인 연마패드와 화학적인 식각 작용을 하는 슬러리를 이용하여 연마가 진행되므로 공정 결함이 문제시되어 왔다. 그 중에서도, 소모자재의 비용이 CMP 공정비용의 70% 이상을 차지하는 제조단가가 높다는 단점이 있다. 특히 고가의 슬러리가 차지하는 비중이 40% 이상을 넘고 있어, 슬러리 원액의 소모량을 줄이기 위한 연구들이 현재 활발히 연구 중에 있다. 본 논문에서는 새로운 혼합 연마제 슬러리에 대한 CMP 특성을 통해 기존에 상용화된 슬러리의 CMP 특성과 비교 고찰하여 MAS의 우수성을 입증하고, 최적화된 공정기술 연구의 기반으로 활용하고자 실리카 슬러리에 $MnO_2$ 연마제를 혼합하여 연마특성을 비교분석하였고, AFM, EDX, XRD, TEM분석을 통해 그 가능성을 알아보았다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11a
• /
• pp.181-184
• /
• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.