• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.647-648
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• 2005

The development of CMP slurry chemistry for Ni that provides good CMP performance is the key for nickel based MEMS device fabrication. In this study, CMP of nickel was performed using different slurry versus oxidizer ratios arid different oxidizers also alumina particles as an abrasive.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.114-118
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• 2009

PVA (polyvinyl alcohol) brush cleaning method is a typical cleaning method for semiconductor cleaning process especially post-CMP cleaning. PVA brush contacts with the wafer surface and abrasive particle, generating the contact rotational torque of the brush, which is the removal mechanism. The brush rotational torque can overcome theoretically the adhesion force generated between the abrasive particle and wafer by zeta potential. However, after CMP (chemical mechanical polishing) process, many particles remained on the wafer because the brush was contaminated in previous post-CMP cleaning step. The abrasive particle on the brush redeposits to the wafer. The level of the brush contamination increased according to the cleaning run time. After cleaning the brush, the level of wafer contamination dramatically decreased. Therefore, the brush cleanliness effect on the cleaning performance and it is important for the brush to be maintained clearly.

• Journal of the Korea Society for Simulation
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• v.11 no.1
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• pp.23-30
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• 2002

An STI(Shallow Trench Isolation) by using a CMP(Chemical Mechanical Polishing) process has been one of the key issues in the device isolation[1] In this paper we fabricated N, P-MOSFEET tall analyse hump characteristics in various rounding oxdation thickness(ex : Skip, 500, 800, 1000$\AA$). As a result we found that hump occurred at STI channel edge region by field oxide recess. and boron segregation(early turn on due to boron segregatiorn at channel edge). Therefore we improved that hump occurrence by increased oxidation thickness, and control field oxide recess( 20nm), wet oxidation etch time(19HF,30sec), STI nitride wet cleaning time(99HF, 60sec+P 90min) and fate pre-oxidation cleaning time (U10min+19HF, 60sec) to prevent hump occurring at STI channel edge.

• BioChip Journal
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• v.16
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• pp.82-98
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• 2020

We report a quantitative and systematic method for determining 3D-printing and surface-treatment conditions that can help improve the optical quality of direct-printed microfluidic devices. Digital light processing (DLP)-stereolithography (SLA) printing was extensively studied in microfluidics owing to the rapid, one-step, cleanroom-free, maskless, and high-definition microfabrication of 3D-microfluidic devices. However, optical imaging or detection for bioassays in DLP-SLA-printed microfluidic devices are limited by the translucence of photopolymerized resins. Various approaches, including mechanical abrasions, chemical etching, polymer coatings, and printing on transparent glass/plastic slides, were proposed to address this limitation. However, the effects of these methods have not been analyzed quantitatively or systematically. For the first time, we propose quantitative and methodological determination of 3D-printing and surface-treatment conditions, based on optical-resolution analysis using USAF 1951 resolution test targets and a fluorescence microbead slide through 3D-printed coverslip chips. The key printing parameters (resin type, build orientation, layer thickness, and layer offset) and surface-treatment parameters (grit number for sanding, polishing time with alumina slurry, and type of refractive-index-matching coatings) were determined in a step-wise manner. As a result, we achieved marked improvements in resolution (from 80.6 to 645.1 lp/mm) and contrast (from 3.30 to 27.63% for 645.1 lp/mm resolution). Furthermore, images of the fluorescence microbeads were qualitatively analyzed to evaluate the proposed 3D-printing and surface-treatment approach for fluorescence imaging applications. Finally, the proposed method was validated by fabricating an acoustic micromixer chip and fluorescently visualizing cavitation microstreaming that emanated from an oscillating bubble captured inside the chip. We expect that our approach for enhancing optical quality will be widely used in the rapid manufacturing of 3D-microfluidic chips for optical assays.

• Journal of the Korean Ceramic Society
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• v.40 no.1
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• pp.77-80
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• 2003

Adsorption of glycine on$Si_3N_4$powder surface has been investigated, which is supposed to enhance the formation of passive layer inhibiting oxidation in aqueous solution. In the basic solution, multinuclear surface complexing between Si and dissociated ligands was responsible for the saturated adsorption of glycine. In addition, $CeO_2$-based CMP slurry containing glycine was manufactured and then applied to planarize$SiO_2$and$Si_3N_4$thin film. Owing to the passivation by glycine, the removal rates, Rh, were decreased, however, the selectivities, RE(SiO$_2$)/RR($Si_3N_4$), increased and showed maximum at pH=12. The suppressed oxidation and dissolution by adsorbate were correlated with the dissociation behavior of glycine at different pH and subsequent chemical adsorption.

• Korean Journal of Materials Research
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• v.14 no.8
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• pp.542-546
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• 2004

We report a new fabrication process for high performance triode type CNT field emitters and their superior electrical properties. The CNT-based triode-type field emitter structure was fabricated by the conventional semiconductor processes. The keys of the fabrication process are spin-on-glass coating and trim-and-leveling of the carbon nanotubes grown in trench structures by employing a chemical mechanical polishing process. They lead to strong adhesion and a uniform distance from the carbon nanotube tips to the electrode. The measured emission property of the arrays showed a remarkably uniform and high current density. The gate leakage current could be remarkably reduced by coating of thin $SiO_{2}$ insulating layer over the gate metal. The field enhancement factor(${\beta}$) and emission area(${\alpha}$) were calculated from the F-N plot. This process can be applicable to fabrication of high power CNT vacuum transistors with good electrical performance.

• Journal of IKEEE
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• v.19 no.1
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• pp.41-44
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• 2015

Silicon trench process for bulk fin field effect transistor (finFET) is suggested without using chemical mechanical polishing (CMP) that cause contamination problems with chemical stuff. This process uses thickness difference of photo resistor spin coating and silicon nitride sacrificial layer. Planarization of silicon oxide and silicon trench formation can be performed with etching processes. In this work 50 nm silicon trench is fabricated with AZ 1512 photo resistor and process results are introduced.

• Korean Journal of Metals and Materials
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• v.47 no.11
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• pp.748-753
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• 2009

The surface morphology and the surface roughness of n-type SiC induced by wet-treatment using 45% KOH and buffered oxide etchant (BOE-1HF : $6H_2O$) were investigated by atomic force microscopy (AFM). While Si-face of SiC could be etched by alkali solutions such as KOH, acidic solutions such as BOE were hardly able to etch SiC. When the rough SiC samples were used, the surface roughness of etched sample was decreased after wet-treatment regardless of etchant, due to the planarization the of surface by widening of scratches formed by mechanical polishing. It was observed that the initial etching was affected by the energetically unstable sites, such as dangling bond and steps. However, when a relatively smooth sample was used, the surface roughness was rapidly increased after treatment at $180^{\circ}C$ for 1 hr and at room temperature for 4 hr by using KOH solution, resulting from the nano-sized structures such as pores and bumps. This indicates that porous SiC surface can be achieved by using purely chemical treatment.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.63-63
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• 2003

The nanotopography of silicon wafers has emerged as an important factor in the STI process since it affects the post-CMP thickness deviation (OTD) of dielectric films. Ceria slurry with surfactant is widely applied to STI-CMP as it offers high oxide-to-nitride removal selectivity. Aiming to control the nanotopography impact through ceria slurry characteristics, we examhed the effect of surfactant concentration and abrasive size on the nanotopography impact. The ceria slurries for this study were produced with cerium carbonate as the starting material. Four kinds of slurry with different size of abrasives were prepared through a mechanical treatment The averaged abrasive size for each slurry varied from 70 nm to 290 nm. An anionic organic surfactant was added with the concentration from 0 to 0.8 wt %. We prepared commercial 8 inch silicon wafers. Oxide Shu were deposited using the plasma-enhanced tetra-ethyl-ortho-silicate (PETEOS) method, The films on wafers were polished on a Strasbaugh 6EC. Film thickness before and after CMP was measured with a spectroscopic ellipsometer, ES4G (SOPRA). The nanotopogrphy height of the wafer was measured with an optical interferometer, NanoMapper (ADE Phase Shift)

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.380-381
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• 2006

Chemical mechanical polishing (CMP) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, the cost of ownership and cost of consumables are relatively high because of expensive slurry. In this paper, we studied the mixed abrasive slurry (MAS). In order to save the costs of slurry, the original silica slurry was diluted by de-ionized water (DIW). And then, $ZrO_2$, $CeO_2$, and $MnO_2$ abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry. We have also investigate the possibility of mixed abrasive slurry for the oxide CMP application.