• Journal of the Korean Vacuum Society
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• 제7권2호
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• pp.88-93
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• 1998

The fabrication process and emission characteristics of gated silicon field emitter arrays(FEAs) using chemical-mechanical-polishing (CMP) method are described. Novel fabrication techniques consisting of two-step dry etching with oxidation of silicon and CMP processes were developed for the formation of sharp tips and clear-cut edged gate electrodes, respectively. The gate height and aperture could be easily controlled by varying the polishing time and pressure in the CMP process. We obtained silicon FEAs having self-aligned and clear-cut edged gate electrode opening by eliminating the dishing problem during the CMP process with an oxide mask layer. The tip height of the finally fabricated FEAs was about 1.1 $\mu$m and the end radius of the tips was smaller than 100 $\AA$. The emission current meaured from the fabricated 2809 tips array was about 31 $\mu$A at a gate voltage of 80 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.38-39
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• 2005

We have investigated the effect of the pad surface characteristics such as roughness, groove density and wear of pad on within wafer non-uniformity(WIWNU) in chemical mechanical polishing(CMP). We found that WIWNU increases as pad surface roughness($R_{pk}$; Reduced peak height) increases in an early stage of polishing. But after polishing time goes to a certain extent, WIWNU decreases as uniformity of pad surface roughness. Also, groove of pad has effect on relative pad stiffness although original mechanical properties of pad are unchanged by grooving. WIWNU decreases as relative pad stiffness decreases. In addition, conditioning process causes non-uniform wear of pad during in CMP. The profile of pad wear has a significant effect on WIWNU.

• Journal of the Korean Society of Manufacturing Process Engineers
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• 제2권4호
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• pp.17-24
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• 2003

Chemical mechanical polishing(CMP) has been applied for planarization of topography after patterning process in semiconductor fabrication process. Tungsten CMP is necessary to build up interconnects of semiconductor device. But the tungsten dishing and the oxide erosion defects appear at end-point during tungsten CMP. It has been known that the generation of dishing and erosion is based on the over-polishing time, which is determined by pattern selectivity. Fixed abrasive pad takes advantage of decreasing the defects resulting flam reducing pattern selectivity because of the lower abrasive concentration. The manufacturing technique of fixed abrasive pad using hydrophilic polymers is introduced in this paper. For application to tungsten CMP, chemicals composed of oxidizer, catalyst, and acid were developed. In comparison of the general pad and slurry for tungsten CMP, the fixed abrasive pad and the chemicals resulted in appropriate performance in point of removal rate, uniformity, material selectivity and roughness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제18권6호
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• pp.521-526
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• 2005

Within wafer non-uniformity(WIWNU) improves as the stiffness of pad decrease. We designed the pad groove to study of pad stiffness on WIWNU in Chemical mechanical polishing(CMP) and measured the pad stiffness according to groove width. The groove influences effective pad stiffness although original mechanical properties of pad are unchanged by grooving. Also, it affects the flow of slurry that has an effect on the lubrication regime and polishing results. An Increase of the apparent contact area of pad by groove width results in decrease of effective pad stiffness. WIWNU and profile of removal tate improved as effective pad stiffness decreased. Because grooving the pad reduce its effective stiffness and it makes slurry distribution to be uniform. Futhermore, it ensures that pad conforms to wafer-scale flatness variability. By grooving the top pad, it is possible to reduce its stiffness and hence reduce WIWNU and edge effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제16권12S호
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• pp.1181-1186
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• 2003

Chemical Mechanical Polishing (CMP) is an essential dielectric planarization in multilayer microelectronic device fabrication. In the CMP process, it is necessary to minimize the extent of surface defect formation while maintaining good planarity and optimal material removal rates. The polishing mechanism of W-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. Thus, it is important to understand the effect of oxidizer on W passivation layer, in order to obtain higher removal rate (RR) and very low non-uniformity (NU %) during W-CMP process. In this paper, we compared the effects of oxidizer or W-CMP process with three different kind of oxidizers with 5 wt% hydrogen peroxide such as Fe(NO$_3$)$_3$, H$_2$O$_2$, and KIO$_3$. The difference in removal rate and roughness of W in stable and unstable slurries are believed to caused by modification in the mechanical behavior of Al$_2$O$_3$ particles in presence of surfactant stabilizing the slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.81-81
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• 2007

Chemical mechanical polishing (CMP) 공정은 deep 서브마이크론 집적회로의 다층배선구조률 실현하기 위해 inter-metal dielectric (IMD), inter-layer dielectric layers (ILD), pre-metal dielectric (PMD) 층과 같은 절연막 외에도 W, Al, Cu와 같은 금속층을 평탄화 하는데 효과적으로 사용되고 있으며, 다양한 소자 제작 및 새로운 물질 등에도 광범위하게 응용되고 있다. 하지만 Cu damascene 구조 제작으로 인한 CMP 응용 과정에서, 기계적으로 깨지기 쉬운 65 nm의 소자 이하의 구조에서 새로운 저유전상수인 low-k 물질의 도입으로 인해 낮은 하력의 기계적 연마가 필요하게 되었다. 본 논문에서는 전기화학적 기계적 연마 적용을 위해, I-V 특성 곡선을 이용하여 active, passive, transient, trans-passive 영역의 전기화학적 특성을 알아보았으며, Cu 막의 표면 형상을 알아보기 위해 scanning electron microscopy (SEM) 측정과 energy dispersive spectroscopy (EDS) 분석을 통해 금속 화학적 조성을 조사하였다.

• The Magazine of the IEIE
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• 제40권12호
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• pp.46-58
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• 2013

• Electrical & Electronic Materials
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• 제12권10호
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• pp.1-8
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• 1999

• Electrical & Electronic Materials
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• 제12권10호
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• pp.9-18
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• 1999

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.34-37
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• 2004

Recently advancing mobile communication tools and I.T industry, semiconductor device is requested more integrated, faster operation time and more scaled-down. Because of these reasons semiconductor device is requested multilayer interconnection. For the multilayer interconnection chemical mechanical polishing (CMP) becomes one of the most useful process in semiconductor manufacturing process. In this experiment, we focus on understand the characterize and improve the CMP technology by control of slurry flow rate. Consequently, we obtain that optimal flow rate of slurry is 170ml/min, since optimal conditions are less chemical flow and performance high with good selectivity to Ta. If we apply this results to copper CMP process. it is thought that we will be able to obtain better yield.