• Journal of Communications and Networks
• /
• v.15 no.1
• /
• pp.71-76
• /
• 2013

A new class of quantum low-density parity-check (LDPC) codes whose parity-check matrices are dual-containing matrices constructed based on lines of Euclidean geometries (EGs) is presented. The parity-check matrices of our quantum codes contain one and only one 4-cycle in every two rows and have better distance properties. However, the classical parity-check matrix constructed from EGs does not satisfy the condition of dual-containing. In some parameter conditions, parts of the rows in the matrix maybe have not any nonzero element in common. Notably, we propose four families of fascinating structure according to changes in all the parameters, and the parity-check matrices are adopted to satisfy the requirement of dual-containing. Series of matrix properties are proved. Construction methods of the parity-check matrices with dual-containing property are given. The simulation results show that the quantum LDPC codes constructed by this method perform very well over the depolarizing channel when decoded with iterative decoding based on the sum-product algorithm. Also, the quantum codes constructed in this paper outperform other quantum codes based on EGs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.11
• /
• pp.1248-1255
• /
• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.3C
• /
• pp.322-328
• /
• 2009

This paper proposes new simplified sum-product (SSP) decoding algorithm to improve BER performance for low-density parity-check codes. The proposed SSP algorithm can replace multiplications and divisions with additions and subtractions without extra computations. In addition, the proposed SSP algorithm can simplify both the In[tanh(x)] and tanh-1 [exp(x)] by using two quantization tables which can reduce tremendous computational complexity. Moreover, the simulation results show that the proposed SSP algorithm can improve about $0.3\;{\sim}\;0.8\;dB$ of BER performance compared with the existing modified sum-product algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.6
• /
• pp.1355-1362
• /
• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Proceedings of the KIEE Conference
• /
• 2006.07d
• /
• pp.2027-2028
• /
• 2006

추정된 채널 정보를 바탕으로 적용하는 적응형 비트 로딩 방식은, 전력선 통신 시스템의 고속화 및 대용량 데이터 전송을 위해 최근 대두되고 있는 LDPC(Low Density Parity Check) coded OFDM 시스템에 대해, 한정된 주파수 대역과 신호 전력의 효율적 사용을 제공한다. 그러나 적응형 비트로딩 방식은 한정된 수의 일정 SNR(신호대 잡음 전력비) 구간에 대한 mapping 방식으로 적용되기 때문에 송수신 과정에서 추정된 채널 정보를 이용하는 sum-product 복호기가 채널 변화에 민감하게 반응하지 못하는 상황이 발생하며, 결국 송신단에서 채널 추정 결과를 바탕으로 선택된 SNR 범위에 대해서는 실제 수신되는 신호에 대한 SNR과의 차이가 존재하고 시스템의 성능은 그 만큼의 성능 열하로 나타나게 된다. 본 논문에서는 이러한 성능 열하 정도를 시뮬레이션을 통해 확인하였다.

• Journal of Communications and Networks
• /
• v.16 no.5
• /
• pp.479-484
• /
• 2014

In this paper, we consider the construction of cyclic and quasi-cyclic structured q-ary low-density parity-check (LDPC) codes over a designated small field. The construction is performed with a pre-defined sliding-window, which actually executes the regular mapping from original field to the targeted field under certain parameters. Compared to the original codes, the new constructed codes can provide better flexibility in choice of code rate, code length and size of field. The constructed codes over small fields with code length from tenths to hundreds perform well with q-ary sum-product decoding algorithm (QSPA) over the additive white Gaussian noise channel and are comparable to the improved spherepacking bound. These codes may found applications in wireless sensor networks (WSN), where the delay and energy are extremely constrained.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.10C
• /
• pp.758-763
• /
• 2008

We introduce a noise-predictive turbo equalization using noise filter in perpendicular magnetic recording(PMR) channel. The noise filter mitigates the colored noise in high-density PMR channel. In this paper, the channel detectors used are SOVA (Soft Output Viterbi Algorithm) and BCJR algorithm which proposed by Bahl et al., and the outer decoder used is LDPC (Low Density Parity Check) code that is implemented by sum-product algorithm. Two kinds of LDPC codes are experimented. One is the 0.5Kbyte (4336,4096) LDPC code with the code rate of 0.94, and the other is 1Kbyte (8432,8192) LDPC code with the code rate of 0.97.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.415-418
• /
• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems such as WiMAX and WLAN. The conventional DFU which is based on min-sum decoding algorithm needs conversions between two's complement values and sign-magnitude values, resulting in complex hardware. In this paper, a new design of DFU that is based on sign-magnitude arithmetic is proposed to achieve a simplified circuit and high-speed operation.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.12 no.4
• /
• pp.569-574
• /
• 2017

In order to transmit information in a channel environment in which noise exists, a coding technique of information is required. One of the coding techniques used for error detection and correction close to the Shannon limit is Low Density Parity Code(LDPC). LDPC and decoding characteristic features by Sum-product algorithm are matched for the performance to Turbo Code, RA(Repeat Accumulate) code, in case of very long code length of LDPC surpass their performance. This paper explains LDPC coding scheme of image data and decoding scheme, implements LDPC decoder in FPGA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.583-585
• /
• 2016

The recent advances in wireless networks area have led to new techniques, such as small cells or full-duplex (FD) transmission, have also been developed to further increase the network capacity. Particularly, full-duplex communication promises expected throughput gain by doubling the spectrum compared to half-duplex (HD) communication. Because this technique permits one set of frequencies to simultaneously transmit and receive signals. In this paper, we focus on the binary power control for the users and the base stations in full-duplex multiple cellulars wireless networks to obtain optimal sum-rate under the effect interference and noise. We investigate with a scenario in there one carrier is assigned to only one user in each cell and construct a model for this problem. In this work, we apply the binary power control by the its simplification in the implemented algorithm for both uplink and downlink simultaneously to maximize sum data rate of the system. At first, we realize the 2-cells case separately to check the optimal power allocation whether being binary. Then, we carry on with N-cells case in general through properties of binary power control.