• 한국가시화정보학회지
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• 제1권2호
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• pp.47-51
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• 2003

Microfluidic chips such as lab-on-a-chip (LOC) include micro-channels for sample delivery, mixing, reaction, and separation. Pressure driven flow or electro-osmotic flow (EOF) has been usually employed to deliver bio-samples. Having some advantages of easy control, the flow characteristics of EOF in microchannels should be fully understood to effectively control the electro-osmotic pump for bio-sam-pie delivery. In this study, a micro PIV system with an epifluorescence inverted microscope and a cooled CCD was used to measure velocity fields of EOF in a glass microchannel and a PDMS microchannel. The EOF velocity fields were changed with respect to electric charge of seeding particles and microchannel materials used. The EOF has nearly uniform velocity distribution inside the microchannel when pressure gradient effect is negligible. The mean streamwise velocity is nearly proportional to the applied electric field. Glass microchannels give better repeatability in PIV results, compared with PDMS microchannels which are easy to fabricate and more suitable for PIV experiments.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.489-492
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• 2000

A novel low-cost simple and unity-power-factor electronic ballast is presented. The proposed electronic ballast employs a bypassing capacitor and load networks composed of ballast capacitors and small charge pump capacitors as power factor correction circuit combined with the secondary winding of the transformer in the self-excited current-fed push-pull resonant inverter(CF-PPRI) resulting in cost-effectiveness and higher efficiency. By analyzing the principles of power factor correction mathematically optimum design guidelines are presented. Since the lamps are used in power factor correction stage the input power is automatically adjusted according to the number of the lamps.

• Journal of Power Electronics
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• 제7권4호
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• pp.294-300
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• 2007

This paper deals with a design of a bootstrap power supply using snubber energy regeneration, which is used to power a high-side gate driver of a half-bridge circuit. In the proposed circuit, the energy stored in the low-side snubber capacitor is transferred to the high-side bootstrap capacitor without any magnetic components. Thus, the power dissipation in the RCD snubber can be effectively reduced. The operation principle and design method of the proposed circuit are presented. The experimental results are also provided to show the validity of the proposed circuit.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2002년도 하계학술대회 및 세미나
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• pp.27-30
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• 2002

10-bit 해상도, 10MS/s의 ADC를 Stage 당 1.5-Bit의 Resolution을 가지는 Redundant signed digit(RSD) 방식의 파이프라인 구조를 이용하여 설계하였다. Error Correction Logic을 사용함으로써 비교기를 Coarse하게 설계하였고 잔류 전압 증폭기의 최적 Scaling을 통하여 일반적인 ADC에 비해 성능 저하 없이 효율적으로 소비 전력을 감소시켰다. 또한, Charge Pump의 선택적 사용을 통해 기생 커패시턴스의 영향을 최소화함으로써 잔류전압 증폭기의 출력 전압 특성을 향상 시켰다. 삼성 0.35u CMOS 공정 파라미터를 이용하여 입력 전압 $-1{\sim}1V$, 공급 전압 $-1.5{\sim}1.5V$에서 18.73mW로 설계하였으며 HSPICE로 시뮬레이션 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.523-526
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• 2001

In this paper, we design and fabricate the high-efficiency and low-power switched-capacitor DC-DC converter. This converter consists of internal oscillator, output driver and output switches. The internal oscillator has 100kHz oscillation frequency and the output switches composed of one pMOS transistor and three nMOS transistors. According to the configuration of two external capacitors, the converter has three functions that are the Inverter, Doubler and Divider. The proposed converter is fabricated through the 0.8$\mu\textrm{m}$ 2-poly, 2-metal CMOS process. The simulation and experimental result for fabricated IC show that the proposed converter has the voltage conversion efficiency of 98% and power efficiency more than 95%.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.1132-1135
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• 2002

In this paper, we propose a phase-locked loop (PLL) with dual loops in which advantages of both loops can be combined. Frequency-locked loop (FLL) which is composed of two frequency-to-voltage converters (FVC) and an amplifier makes the frequency synchronize very fast and output signal is synchronized in phase with the input reference signal by charge pump PLL. This structure can improve the trade-off between acquisition behavior and locked behavior.

• 전자공학회논문지A
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• 제33A권10호
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• pp.115-122
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• 1996

A 300MHz PLL including FVC (frequency to voltage converter) is designed and fabricated in 0.8$\mu$m CMOS process. In this design, a FVC and a 2nd - order passive filter are added to the conventional charge-pump PLL to improve the acquisition time. The dual-rijng VCO(voltage controlled oscillator) realized in this paper has a frequency range form 208 to 320MHz. Integrated circuits have been fully tested and analyzed in detail and it is proved that pull-in speed is enhanced with the use fo FVC. In VCO range from 230MHz to 310MHz, experimental results show that realized PLL exhibits 4 times faster pull-in speed than that of conventional PLL.

• 마이크로전자및패키징학회지
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• 제8권1호
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• pp.19-25
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• 2001

본 연구에서는 디지털 셀룰러용 IF Frequency Synthesizer의 설계, 시뮬레이션 결과 및 측정 결과를 기술하였으며, 공정 및 소자 라이브러리는 AMS사의 0.8 $\mu\textrm{m}$ BiCMOS를 사용하였다. IF Frequency Synthesizer부는 IF 전압제어발진기, 위상검파기, 8분배기, 차지 펌프 및 루프 필터(Loop Filter) 등을 포함하고 있다. 공급전원은 2.7에서 3.6 V이며, IF VCO의 조절전압은 0.5~2.7V이고, 소비전류는 11 mA로 설계결과와 측정결과가 유사한 결과를 보였다.

• 한국초전도ㆍ저온공학회논문지
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• 제17권3호
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• pp.18-22
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• 2015

This paper deals with high-Tc superconducting (HTS) power charging system with GdBCO magnet, photo-voltaic (PV) controller, and solar panels to charge solar energy. When combining the HTS magnet and the solar energy charging system, additional power source is not required therefore it is possible to obtain high power efficiency. Since there is no resistance in superconducting magnet carrying DC transport current the energy losses caused by joule heating can be reduced. In this paper, the charging characteristics of HTS power charging system was simulated by using PSIM. The charging current of HTS superconducting power charging system is measured and compared with the simulation results. Using the simulation of HTS power charging system, it can be applied to the solar energy applications.

• Journal of Information Display
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• 제9권2호
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• pp.9-13
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• 2008

A novel push-pull voltage converter structure, using a switched capacitor type voltage doubler, is proposed. The circuit is constructed with a two-stage push-pull voltage doubler that has a stable operation with small output ripple. The two-stage voltage doubler creates the output voltage 4Vdd. The high clock signal is cross-coupled to the input of the second stage with the opposite phase to reduce two switching transistors and capacitors. Simulation results verify that even with a reduced number of transistor and capacitor, there is no circuit performance loss. Adding one capacitor and two switching transistors the circuit can be changed to eight times of Vdd maker.