• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.806-808
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• 1992

This paper describes a buried-island SOI MOSFET structure which can reduce the edge channel effect by improving the interface properties at the side wall of active island and by reducing the strength of electric field applied at the upper corner of the side wall from the gate. Also, the buried-island SOl structure can obtain the uniform thickness of SOl film. The buried-island structure can be achieved by Zone- Melting-Recrystallization of polysilicon and polishing. Both simulated and experimental results show that the buried-island SOl NMOSFET has less edge channel effect than the conventional SOl NMOSFET using LOCOS or mesa isolation technique.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.921-926
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• 2001

The link for the Superconducting Flux Flow Transistor (SFFT) which is based on the flux flow has been fabricated by the ICP etching methods. The channel width and the thickness of the SFFT were a 3 ${\mu}$m and about 300 nm, respectively. The superconducting characteristic of the link was measured by the x-ray diffraction and the E.D.S.. The SFFT etched by ICP showed an I-V characteristic like the three terminal transistor.

• 한국전기전자재료학회논문지
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• 제21권10호
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• pp.930-933
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• 2008

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40 nm, and the channel length was $50{\mu}m$, channel width was 3 mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.389-390
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• 2008

We fabricated organic field-effect transistors (OFETs) based a fluorinated copper phthalocyanine ($F_{16}CuPc$) as an active layer. And we observed the surface morphology of the $F_{16}CuPc$ thin film. The $F_{16}CuPc$ thin film thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in $F_{16}CuPc$ FET and we calculated the effective mobility.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.410-411
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• 2008

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• 한국공작기계학회논문집
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• 제17권1호
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• pp.59-64
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• 2008

Micro machining can manufacture complex shapes with high accuracy. Especially, this enables wide application of micro technology in various fields. For example, micro channels allow fluid transfer, which is a widely used technology. Therefore, liquidity research of flow in micro channels and micro channel manufacturing with use of various materials and cutting conditions has very important meaning. In this study, to find out correlation between fluid velocity in micro channels and surface roughness, we manufactured micro channels using micro end-mill and dropped ethanol into micro channels. We compared several surface roughness and fluid velocity in micro channels that were created by various processing conditions. Finally, we found out relationship between fluid velocity and surface roughness in micro channels of different materials.

• 동력기계공학회지
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• 제13권1호
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• pp.5-12
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• 2009

The present work aims to estimate channel, shell, tube and tube sheet stresses of shell and tube oil cooler stemmed from various parameters. These parameters involve size, thickness and dimension of shell and tube oil cooler, including fluid temperature. The main purpose of the present work is to ensure safety of design products and also develop new products rapidly. For stress evaluation of oil coolers, first of all, the maximum pressure on the shell-side and on the tube side is fixed with 3.1MPa and 1.5MPa, respectively. Secondly, the pressure on each side varies from 2MPa to 3.1MPa on the shell side and tram 0.6MPa to 2MPa on the tube side. Various parameters under these conditions are employed to estimate design stresses on each side of oil cooler. These basic information related to stresses will be useful for a designer or manufacturer of an oil cooler.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 춘계학술대회 논문집
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• pp.43-44
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• 2009

We fabricated organic field-effect transistors (OFETs) based a fluorinated copper phthalocyanine ($F_{16}CuPc$) as an active layer. And we observed the surface morphology of the $F_{16}CuPc$ thin film. The $F_{16}CuPc$ thin film thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in $F_{16}CuPc$ FET and we calculated the effective mobility.

• Journal of information and communication convergence engineering
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• 제7권3호
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• pp.361-365
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• 2009

This paper has been presented the transport characteristics of FinFET using the analytical potential model based on the Poisson's equation in subthreshold and threshold region. The threshold voltage is the most important factor of device design since threshold voltage decides ON/OFF of transistor. We have investigated the variations of threshold voltage and drain induced barrier lowing according to the variation of geometry such as the length, width and thickness of channel. The analytical potential model derived from the three dimensional Poisson's equation has been used since the channel electrostatics under threshold and subthreshold region is governed by the Poisson's equation. The appropriate boundary conditions for source/drain and gates has been also used to solve analytically the three dimensional Poisson's equation. Since the model is validated by comparing with the three dimensional numerical simulation, the subthreshold current is derived from this potential model. The threshold voltage is obtained from calculating the front gate bias when the drain current is $10^{-6}A$.