• ETRI Journal
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• 제11권2호
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• pp.109-119
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• 1989

Based on the 2-dimensional charge-control simulation[4], a purely analytical model for MODFET's is proposed. In this model, proper treatment of the diffusion effect in the 2-DEG transport due to the gradual channel opening along the 2-DEG channel was made to explain the enhanced mobility and increased thershold voltage. The channel thickness and gate capacitance are experssed as functions of gate vlotage including subthreshold characteristics of the MODFET's analytically. By introducing the finite channel opening and an effective channel-length modulation, the slope of the saturation region of the I-V curves was modeled. The smooth transition of the I-V curves from linear-to-saturation region of the I-V curves was possible using the continuous Troffimenkoff-type of field-dependent mobility. Furthermore, a correction factor f was introduced to account for the finite transtition section forming between the GCA and the saturated section. This factor removes the large discrepanicies in the saturation region fo the I-V curves presicted by existing 1-dimensional models. The fitting parameters chosen in our model were found to be predictable and vary over relatively small range of values.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회B
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• pp.2544-2547
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• 2008

A micro channel heat sink has been studied and optimized for mixed pressure driven and electroosmotic flows through three-dimensional numerical analysis. The effects of ionic concentration represented by zeta potential and Debye thickness are studied with the various steps of externally applied electric potential. Optimization of the micro channel heat sink has been performed considering two design variables related to the micro channel width, depth and fin width. The surrogate-based optimization is performed using a search algorithm taking overall thermal resistance as objective function. The thermal resistance is found to be more sensitive to channel width-to-depth ratio than fin width-to-depth of channel ratio.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.45-49
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• 2007

The analytical transport model in subthreshold regime for double gate MOSFET has been presented to analyze the short channel effects such as subthreshold swing, threshold voltage roll-off and drain induced barrier lowering. The present approach includes the quantum tunneling of carriers through the source-drain barrier. Poisson equation is used for modeling thermionic emission current, and Wentzel-Kramers-Brillouin approximations are applied for modeling quantum tunneling current. This model has been used to investigate the subthreshold operations of double gate MOSFET having the gate length of the nanometer range with ultra thin gate oxide and channel thickness under sub-20nm. Compared with results of two dimensional numerical simulations, the results in this study show good agreements with those for subthreshold swing and threshold voltage roll-off. Note the short channel effects degrade due to quantum tunneling, especially in the gate length of below 10nm, and DGMOSFETs have to be very strictly designed in the regime of below 10nm gate length since quantum tunneling becomes the main transport mechanism in the subthreshold region.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2003년도 하계학술대회 논문집
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• pp.110-113
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• 2003

In this paper, the multi-channel high speed data acquisition system is implemented. This high speed signal processing system for 3-D image display is applicable to the manipulation of a medical image processing, multimedia data and various fields of digital image processing. In order to convert the analog signal into digital one, A/D conversion circuit is designed. PCI interface method is designed and implemented, which is capable of transmission a large amount of data to computer. In order to, especially, channel extendibility of images acquisition, bus communication method is selected. By using this bus method, we can interface each module effectively. In this paper, 32-channel A/D conversion and PCI interface system for 3-dimensional and real-time display of the retina image is developed. The 32-channel image acquisition system and high speed data transmission system developed in this paper is applicable to not only medical image processing as 3-D representation of retina image but also various fields of industrial image processing in which the multi-point realtime image acquisition system is needed.

• 한국산업융합학회 논문집
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• 제24권6_1호
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• pp.683-691
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• 2021

Bipolar plates with channel width of 0.5 mm, 0.4 mm, and 0.3 mm respectively were printed using a 3D printer. The shape of three b ipolar plates was rectangular, the channel depth was 0.5 mm, and the thickness of base was 0.5 mm. The bipolar plate with channel width of 0.5 mm had 45 channels, and their active area was 44.5 mm × 50 mm. The bipolar plate with channel width of 0.4 mm had 57 channels and its active area was 45.2 mm × 50 mm, and the bipolar plate with channel width of 0.3 mm had 75 channels and its active area was 44.7 mm × 50 mm. The bipolar plates were printed using PLA filament. The cross-sectional lengths of the bipolar plates with channel widths of 0.5 mm and 0.4 mm were identical by 96% of the designed cross-sectional length. Whereas the bipolar plate with a channel length of 0.3 mm had a large difference of 25% from the designed cross-sectional length.

• 전기전자학회논문지
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• 제22권1호
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• pp.74-79
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• 2018

본 논문에서는 무접합 원통형과 무접합 이중게이트 MOSFET의 중심전위와 문턱전압이하 스윙의 관계를 분석하였다. 해석학적 전위분포를 이용하여 문턱전압이하 스윙을 구하고 중심전위와 문턱전압이하 스윙을 채널크기 변화에 따라 비교 고찰하였다. 결과적으로 중심전위분포의 변화가 직접적으로 문턱전압이하 스윙에 영향을 미치고 있다는 것을 관찰하였다. 채널두께나 산화막 두께가 증가할수록 문턱전압이하 스윙은 증가하였으며 JLDG 구조가 더욱 민감하게 증가하였다. 그러므로 나노구조 MOSFET의 단채널효과를 감소시키기 위하여 JLCSG 구조가 더욱 효과적이라는 것을 알 수 있었다.

• 한국정보통신학회논문지
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• 제16권10호
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• pp.2267-2272
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• 2012

본 연구에서는 이중게이트 MOSFET에서 스켈링 이론에 대한 문턱전압이하 스윙을 분석하였다. 포아송방정식의 해석학적 전위분포를 구하기 위하여 가우스 전하분포를 이용하였다. 문턱전압이하 스윙의 저하와 같은 단채널 효과를 분석하기 위하여 스켈링이론이 사용되었으며 이중게이트 MOSFET의 특성상 두 개의 게이트 효과를 포함하기 위하여 일반적인 스켈링 이론을 수정하였다. 게이트길이에 대한 스켈링인자가 일반적인 스켈링인자의 1/2일 때 문턱전압이하 스윙의 저하현상이 매우 빠르게 감소하였으며 가우스함수의 이온주입범위 및 분포편차도 문턱전압이하 스윙에 영향을 미치는 것을 알았다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 추계학술대회논문집B
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• pp.591-596
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• 2000

Flow through compliant tubes with linear taper in wall thickness is numerically simulated by finite element analysis. Two models are examined: a planar two-dimensional channel, and an axisymmetric tube. For verification of the numerical method, flow through a compliant stenotic vessel is simulated and compared to existing experimental data. Computational results for an axisymmetric tube show that as cross-sectional area falls with a reduction in downstream pressure, flow rate increases and reaches a maximum when the speed index (mean velocity divided by wave speed) is near unity at the point of minimum cross-section area, indicative of wave speed flow limitation or "choking" (flow speed equals wave speed) in previous one-dimensional studies. For further reductions in downstream pressure, flow rate decreases. Cross-sectional narrowing is significant but localized. When the ratio of downstream-to-upstream wall thickness is ${\le}$ 2 the area throat is located near the downstream end; as wall taper is increased to ${\ge}$ 3 the constriction moves to the upstream end of the tube. In the planar two-dimensional channel, area reduction and flow limitation are also observed when outlet pressure is decreased. In contrast to the axisymmetric case, however, the elastic wall in the two-dimensional channel forms a smooth concave surface with the area throat located near the mid-point of the elastic wall. Though flow rate reaches a maximum and then falls, the flow does not appear to be choked.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2006년도 춘계종합학술대회
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• pp.861-864
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• 2006

본 연구에서는 분석학적 모델을 이용하여 나노구조 이중게이트 MOSFET의 전도현상을 고찰하고자 한다. 분석학적모델을 유도하기 위하여 포아슨방정식을 이용하였다. 전류전도에 영향을 미치는 전도메카니즘은 열방사전류와 터널링전류를 사용하였으며 본 연구의 모델이 타당하다는 것을 입증하기 위하여 서브문턱스윙값에 대하여 이차원 시뮬레이션값과 비교하였다. 이중게이트 MOSFET의 구조적 파라미터인 게이트길이, 게이트 산화막 두께, 채널두께에 따라 전도중심의 변화와 전도중심이 서브문턱 스윙에 미치는 영향을 고찰하였다. 또한 채널도핑농도에 따른 전도중심의 변화를 고찰함으로써 이중 게이트 MOSFET의 타당한 채널도핑농도를 결정하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.