• BMB Reports
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• v.28 no.2
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• pp.184-190
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• 1995

Functional study of the gap junction channel has been hindered by its inaccessibility in situ. Identification of forms of this channel in artificial membrane has been elusive because of the lack of identifying channel physiology. Connexin32 forms gap junction channels between neighboring cells in rat liver. Connexin32 was affinity-purified using a monoclonal antibody and reconstituted into artificial phospholipid vesicles. The reconstituted connexin32 formed channels through the vesicle membrane that were permeable to sucrose (Stokes radius: $5{\AA}$). The permeability to sucrose was reversibly reduced by acidic pH. In addition, the pH effect on the permeability to sucrose fit well with by the Hill's equation (where, n=2.7 and pK=6.7).

• Journal of Communications and Networks
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• v.12 no.4
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• pp.317-329
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• 2010

In recent years, many sparse estimation methods, also known as compressed sensing, have been developed. However, most of these methods presume that the measurement matrix is completely known. We develop a new blind maximum likelihood method-the expectation-sparse-maximization (ESpaM) algorithm-for models where the measurement matrix is the product of one unknown and one known matrix. This method is a variant of the expectation-maximization algorithm to deal with the resulting problem that the maximization step is no longer unique. The ESpaM algorithm is justified theoretically. We present as well numerical results for two concrete examples of blind channel identification in digital communications, a doubly-selective channel model and linear time invariant sparse channel model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.10A
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• pp.930-937
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• 2005

In this paper, a processing time and traffic capacity analysis algorithm for RFID system using LBT-serial searching scheme is proposed. Service time, carrier sensing time, additional delay time required for contiguous frequency channel occupancy, and additional delay time required for the contiguous using the same frequency channel are considered and the processing delay and frequency channel capacity are analyzed for the steady state operation of the system. The simulation results showing maximum capacity of the system and explaining the accuracy of the algorithm are provided.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.366-366
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• 2000

In this paper, an adaptive neuro-fuzzy filter using the conditional fuzzy c-means(CFCM) methods is proposed. Usualy, the number of fuzzy rules exponentially increases by applying the grid partitioning of the input space, in conventional adaptive neuro-fuzzy inference system(ANFIS) approaches. In order to solve this problem, CFCM method is adopted to render the clusters which represent the given input and output data. Parameter identification is performed by hybrid learning using back-propagation algorithm and total least square(TLS) method. Finally, we applied the proposed method to the nonlinear channel equalization problem and obtained a better performance than previous works.

• The Korean Journal of Physiology and Pharmacology
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• v.4 no.6
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• pp.427-437
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• 2000

The early studies of cardiac and smooth muscle cells provided evidence for two different calcium channels, the L-type (also called high-voltage activated [HVA]) and T-type (low-voltage activated [LVA]). These calcium channels provided calcium for muscle contractions and pace-making activities. As might be expected, the number of different calcium channels increased when researchers studied neurons and the identification of the neuronal calcium channels has proven to be much more difficult than with the muscle calcium channels. There are two reasons for this difficulty; (1) a larger number of different calcium channels in neurons and (2) many of the different calcium channels have similar kinetic properties. This review uses the N-type calcium channel to illustrate the difficulties in identifying and characterizing calcium channels in neurons. It shows that the discovery of toxins that can specifically block single calcium channel types has made it possible to easily and rapidly discern the physiological roles of the different calcium channels in the neuron, Without these toxins it is unlikely that progress would have been as rapid.

• Journal of IKEEE
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• v.14 no.4
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• pp.297-304
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• 2010

This paper presents a link layer design of DisplayPort interface with a state machine based on packet processing. The DisplayPort link layer provides isochronous video/audio transport service, link service, and device service. The merged video, audio main link, and AUX channel controller are implemented with 7,648 LUTs(Loop Up Tables), 6020 register, and 821,760 of block memory bits synthesized using a FPGA board and it operates at 203.32MHz.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.4
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• pp.971-980
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• 2017

Data deduplication can be utilized to reduce storage space in cloud storage services by storing only a single copy of data rather than all duplicated copies. Users who are concerned the confidentiality of their outsourced data can use secure encryption algorithms, but it makes data deduplication ineffective. In order to reconcile data deduplication with encryption, Liu et al. proposed a new server-side cross-user deduplication scheme by exploiting password authenticated key exchange (PAKE) protocol in 2015. In this paper, we demonstrate that this scheme has side channel which causes insecurity against the confirmation-of-file (CoF), or duplicate identification attack.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.51 no.2
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• pp.178-186
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• 2018

A chirp-echo data acquisition and processing system was developed for use as a simplified, PC-based chirp echo-sounder with some data processing software modules. The design of the software and hardware system was implemented via a field-programmable gate array (FPGA). Digital signal processing algorithms for driving a single-channel chirp transmitter and dual-channel receivers with independent TVG (time varied gain) amplifier modules were incorporated into the FPGA for better real-time performance. The chirp-echo data acquisition and processing system consisted of a notebook PC, an FPGA board, and chirp sonar transmitter and receiver modules, which were constructed using three chirp transducers operating over a frequency range of 35-210 kHz. The functionality of this PC-based chirp echo-sounder was tested in various field experiments. The results of these experiments showed that the developed PC-based chirp echo-sounder could be used in the acquisition, processing and analysis of broadband acoustic echoes related to fish species identification.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.402-404
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• 2003

Radio frequency identification (RF-ID) is an automatic data capture (ADC) technology that comprises small data-carrying device(is called Tag) and fixed or mobile device(is called reader). Tags are attached or deattached device. Readers may be installed at locations where data capture is required, and may also be in the form of portable readers. In this paper, we are proposing an application for the subway station using the RF-ID system and a system for the gateless fare collection passing through the booth in only carrying the card. In this system that RF-ID system and Bluetooth are applied. We designed two wireless communication channels. One is the 125kHz communication channel by FSK and PSK for power supplying on the card and identification and the other is 2.4GHz channel for the collection.

• Journal of IKEEE
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• v.15 no.2
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• pp.113-121
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• 2011

This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel transmitter and receiver are implemented with 7,648 LUTs and 6,020 slice register synthesized in Xilinx Vertex4 FPGA and can be operated at 72MHz to support 720Mbps.