• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 추계학술대회 논문집
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• pp.697-698
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• 2010

• 대한전기학회논문지:시스템및제어부문D
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• 제51권9호
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• pp.423-430
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• 2002

The fabrication and experimentation of multi-channel electrodes which enable detecting and recording of multi-site neuronal signals have been investigated. A multi-channel electrode array was fabricated by depositing 2000${\AA}$ thick Au layer on the 1000${\AA}$ thick Ti adhesion layer on a glass wafer. The metal paths were patterned by wet etching and passivated by depositing a PECVD silicon nitride insulation layer to prevent signals from intermixing or cross-talking. After placing a thin slice of rat cerebellar granule cell in the culture ring located in central portion of the multi-channel electrode plate, a neuronal signal from an electrode which is in contact with the cerebellar granule cell has been detected. It was found that the electrode impedance ranges 200㏀∼1㏁ and the impedance is not changed by cleaning with nitric acid. Also, the impedance is inversely proportion to the exposed electrode area and the cross-talk is negligible when the electrode spacing is bigger than 600$\mu\textrm{m}$. The amplitude and frequency of the measured action potential were 38㎷ and 2㎑, which are typical values. From the experimental results, the fabricated multi-channel electrode array proved to be suitable for multi-site neuronal signal detection for the analysis of a complicated cell network.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
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• pp.363-367
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• 1988

A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• Journal of Electrical Engineering and information Science
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• 제2권4호
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• pp.106-110
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• 1997

A new SOI NMOSFET with a 'LOCOS-like' shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication was tried. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3${\mu}{\textrm}{m}$ SOI devices with V\ulcorner of 0.77V and Tox=7.6nm is 360$mutextrm{A}$/${\mu}{\textrm}{m}$ at V\ulcorner\ulcorner=3.5V and V\ulcorner=2.5V. Improved breakdown characteristics were obtained and the BV\ulcorner\ulcorner\ulcorner(the drain voltage for 1 nA/${\mu}{\textrm}{m}$ of I\ulcorner at V=\ulcorner\ulcorner=0V) of the device with L\ulcorner\ulcorner=0.3${\mu}{\textrm}{m}$ under the floating body condition was as high as 3.7 V. Problems for the new scheme are also addressed and more advanced device structure based on the proposed scheme is proposed to solve the problems.

• 한국통신학회논문지
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• 제31권7A호
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• pp.702-708
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• 2006

본 논문에는 초광대역 통신시스템을 위한 주파수 영역의 통계학적 채널 모델을 서술하고 있다. 채널 모렐링은 3개의 사무실 환경, 46개의 송, 수신 위치에서 얻어진 23,000개의 채널응답함수로 부터 얻어졌다. 측정실험을 통해 얻어진 데이터를 바탕으로 주파수 변화에 따른 경로감쇄지수 변화에 대해 서술한 후 전파환경과 가시경로의 존재여부에 따른 수신신호의 확률분포모델을 연구하였다. 마지막으로는 수신된 주파수 톤에 해당하는 수신파워의 표준편차와 같은 통계적 특성들을 고찰하였는데, 가시경로가 존재하는 경우에는 송, 수신기 사이의 거리가 멀어지면서 표준편차 값이 커지고 그에 따라 수신 주파수 톤의 파워가 평균 수신파워에서 일정한 범위 안에 들어올 확률이 떨어지는 것을 알 수 있었다.

• 대한전기학회논문지
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• 제38권6호
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• pp.401-415
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• 1989

A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.

• 한국분말재료학회지
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• 제11권3호
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• pp.233-241
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• 2004

In this study, bottom-up type powder processing and top-down type SPD (severe plastic deformation) approaches were combined in order to achieve both full density and grain refinement of Al-20 wt% Si powders without grain growth, which was considered as a bottle neck of the bottom-up method using the conventional powder metallurgy of compaction and sintering. ECAP (Equal channel angular pressing), one of the most promising method in SPD, was used for the powder consolidation. The powder ECAP processing with 1, 2, 4 and 8 passes was conducted for 10$0^{\circ}C$ and 20$0^{\circ}C$ It was found by microhardness, compression tests and micro-structure characterization that high mechanical strength could be achieved effectively as a result of the well bonded powder contact surface during ECAP process. The SPD processing of powders is a viable method to achieve both fully density and nanostructured materials.

• 한국컴퓨터산업학회논문지
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• 제9권2호
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• pp.77-82
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• 2008

The diversity reception and the equal gain combining technique are applied to the compensation of the distortion of channel, which occurs in transmission of data at rapid speed. DSSS BPSK system which has the receiving structure with the compensation algorithm is formed on the diversity branch, and the characteristics of the system are evaluated at the view point of the average bit error rate due to the SNR. In addition, the multi-tap update algorithm which is superior for the data compensation is suggested. Moreover, using the American Joint Technical Committee PCS RF channel characterization and system deployment model standard, the suggested multi-tap update algorithm is compared and analyzed with the view-point of the average bit error rate and convergence speed for evaluating the realistic efficiency of the system.

• 한국전자파학회논문지
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• 제19권6호
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• pp.688-697
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• 2008

본 논문에서는 실내 환경에서 가시 광선을 이용한 무선 망 설계에 필요한 가시광의 특성 예측을 위해 포톤 모델을 이용하는 방법을 제시한다. 광선을 이용하는 경우, 높은 주파수와 짧은 파장을 갖고 있으므로 광선 추적법을 이용하는 것이 일반적이나, 환경이 복잡하고 복수의 반사, 투과뿐만 아니라 물체 표면의 거친 정도 등의 재질을 고려한 난반사까지 고려해야 하는 경우, 매우 많은 시간이 걸리는 단점이 있다. 이러한 단점을 해결하기 위해 본 논문에서는 광선 추적법을 보완하여 광선의 세기를 포톤의 밀도로 근사하여 계산 정밀도와 계산 시간을 타협하는 방식을 제시한다.