• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.1-11
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• 1997

We developed a base station modulator ASIC for CDMA digital cellular system. In CDMA digital cellular system, the modulation is performed by convolutional encoding and QPSK with spread spectrum. The function blocks of base station modulator are CRC, convolutional encoder, interleaver pseudo-moise scrambler, power control bit puncturing, walsh cover, QPSK, gain controller, combiner and multiplexer. Each function block was designed by the logic synthesis of VHDL codes. The VHDL code was described at register transfer level and the size of code is about 8,000 lines. The circuit simulation and logic simulation were performed by COMPASS tools. The chip (ES-C2212B CMB) contains 25,205 gates and 3 Kbit SRAM, and its chip size is 5.25 mm * 5,45 mm in 0.8 mm CMOS cell-based design technology. It is packaged in 68 pin PLCC and the power dissipation at 10MHz is 300 mW at 5V. The ASIC has been fully tested and successfully working on the CDMA base station system.

• Journal of IKEEE
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• v.21 no.3
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• pp.260-263
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• 2017

Based on several CPU cores, an SoC including ADCs, DC-DC converter and 2M-byte SRAM is proposed in this paper. The CPU core consists of a 12-bit MENSA, a 32-bit Symmetric multi-core processor, as well as 16-bit CDSP. To eliminate the external SDRAM memory, internal 2M-byte SRAM is implemented. Because the SRAM normally occupies huge area, the parasitic components reduce the speed of SoC. In this work, the SRAM blocks are divided into small pieces to reduce the parasitic components. The proposed SoC is developed in a standard 55nm CMOS process and the speed of SoC is 200MHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.1
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• pp.85-91
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• 2014

As RFID is utilized more frequently and diversely in terms of its application areas, the application of mobile RFID technology, which integrates cellular networks and RFID, is highly anticipated. The growth and development of the RFID field has bolstered the development of mobile RFID chips to be embedded in mobile phones. Because mobile RFID chips are embedded in cell phones, limitations such as low power, small form factor, and costliness must be confronted. This study presents the design of a RFID digital baseband processor that is suitable for mobile readers. The RF analog component, which affects the baseband signals, is designed separately, in consideration of the limitations stated above. The function of the baseband processor was verified through simulations and prototyped using FPGA. The power consumption of the chip is 20mW under a 20MHz clock and the chip measures $3mm{\times}3mm$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.586-597
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• 2004

MAC (Medium Access Control) protocol is necessary for a OLT (Optical Line Termination) to allocate bandwidth to ONUs (Optical Network Units) dynamically in ATM PON (Passive Optical Network) operated in a kind of optical subscriber network having tree topology. The OLT collect information about ONUs and provide all permission with each ONU effectively by means of MAC protocol. Major functions of MAC protocol are composed of the algorism for distributing permission demanded by a ONU dynamically and allocation all permission used in APON properly. Sometimes MAC get to be a element of limiting the whole operation speed and occupy a most frequent operation part of the TC (Transmission Convergence) function module so it have to be designed to guarantee the best quality for each traffic. This paper introduce the way of implementation of a algorism which satisfy all of the upper renditions. This MAC algorism allocate bandwidth according to a number of working ONU and the information of the queue length dynamically and distribute permission for same interval to minimize delay variation of each ONU cell. MAC scheduler for the dynamic bandwidth allocation which is introduced in this paper has look-up table structure that makes programming possible. This structure is very suitable for implementation and operated in high speed because it require very simple and small chip size.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.6
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• pp.55-66
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• 2016

Power gating is one of effective techniques for reducing leakage current in semiconductor chip. However, power gating cell (PGC) which is used to switch the power source causes performance degradation and the associated reliability problem by increasing IR drop. However, the newly raised problem caused by different scaling properties between gates and metal wires demands additional considerations in power gating design. In this paper, we propose a robust cell placement based power gating design method for reducing the area for power gating cell and metal routing thus to meet IR drop requirement. Experimental results by applying the proposed techniques on the application processor for smartphone fabricated in 28nm CMOS process show that power gating cell area is reduced by 16.16% and maximum IR drop value is also decreased by 8.49% compared to existing power gating cell placement techniques.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.28-35
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• 2007

In this paper, an ultra low voltage SRAM design method based on dual-boosted cell bias technique is described. For each read/write cycle, the wordline and cell power node of the selected SRAM cells are boosted into two different voltage levels. This enhances SNM(Static Noise Margin) to a sufficient amount without an increase of the cell size, even at sub 1-V supply voltage. It also improves the SRAM circuit speed owing to increase of the cell read-out current. The proposed design technique has been demonstrated through 0.8-V, 32K-byte SRAM macro design in a $0.18-{\mu}m$ CMOS technology. Compared to the conventional cell bias technique, the simulation confirms an 135 % enhancement of the cell SNM and a 31 % faster speed at 0.8-V supply voltage. This prototype chip shows an access time of 23 ns and a power dissipation of $125\;{\mu}W/Hz$.

• Asian Pacific Journal of Cancer Prevention
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• v.14 no.9
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• pp.5513-5518
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• 2013

IFN-${\gamma}$ plays an indirect anti-cancer role through the immune system but may have direct negative effects on cancer cells. It regulates the viability of gastric cancer cells, so we examined whether it affects their proliferation and how that might be brought about. We exposed AGS, HGC-27 and GES-1 gastric cancer cell lines to IFN-${\gamma}$ and found significantly reduced colony formation ability. Flow cytometry revealed no effect of IFN-${\gamma}$ on apoptosis of cell lines and no effect on cell aging as assessed by ${\beta}$-gal staining. Microarray assay revealed that IFN-${\gamma}$ changed the mRNA expression of genes related to the cell cycle and cell proliferation and migration, as well as chemokines and chemokine receptors, and immunity-related genes. Finally, flow cytometry revealed that IFN-${\gamma}$ arrested the cells in the G1/S phase. IFN-${\gamma}$ may slow proliferation of some gastric cancer cells by affecting the cell cycle to play a negative role in the development of gastric cancer.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.1
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• pp.114-122
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• 1997

This paper describes the design and development of a smart digital load cell used forweighing installations. Sice the load cell sensor to be used is very sensitive for weight cariation, the load cell must have the temperature stability, low-drift and the high-resolution of the A/D conversion for accuracy. A new analog circuit which is controlled by one chip micro-processer has been developed to reduce the offset voltage and the drift characteristics of operational amplifiers, and has been adapted into the digital load cell. Also, a software algorithm has been developed to obtain the stable and accurate A/D conversion. This software includes a RS-485 communication program to control the digital load cell, which gives a capability of backing-up the calibration data and transferring control data. The simulation and evaluation of the designed digital load cell has been shown as having the good performance. which will give useful application to the weighing installations as a remote weighing sensor.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.50-59
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• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

• Clean Technology
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• v.21 no.2
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• pp.90-95
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• 2015

Digital microfluidic electroporation system was used for the transformation of microalgae and we have obtained higher transformation efficiency and viability than that of conventional method. Key parameters of electroporation such as pulse voltage, number, and duration time were systematically investigated for two different microalgal strains with and without cell wall. We have found that cell wall does not always have negative effects on the gene transformation of microalgae. Parallel processing of proposed digital microfluidic electroporation was demonstrated together with on chip culture of microalgae.