• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.61-71
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• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

• Clinical and Experimental Pediatrics
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• v.48 no.7
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• pp.779-788
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• 2005

Purpose : Echinacea, a traditional plant medicine has been used as immune-stimulant. Recent studies have revealed that extract of Echinacea has immunostimulatory effects on human blood mononuclear cells. This study was designed for the purpose of screening the genes associated with immunologic effects of Echinacea on monocytes and dendritic cells using a cDNA microarray chip. Methods : $CD14^+$ monocyte cells were cultured for one day with Echinacea extract(final concentration : $50{\mu}g/mL$) in experiment 1, but were cultured without Echinacea in experiment 2. The gene expression of these cultured monocytes was analyzed using the cDNA microarray chip. Dendritic cells produced from $CD14^+$ monocyte were cultured for five days with GM-CSF and IL-4, and then cultured for one day with Echinacea in experiment 3, but were done without Echinacea in experiment 4. Results : In experiments 1 and 2, there were 17 significantly expressed genes with average expression ratios above 2.5, including interferon gamma-inducible protein 30(IFI 30), CDC(cell-division-cylcle)-like kinase 2(CLK 2), syndecan binding protein(syntenin), superoxide dismutase 2, etc. In experiments 3 and 4, there were 24 gene, with significantly expressed genes were 24 genes, which were insulin-like growth factor 2(somatomedin A), methyl-CpG binding domain protein 3, IFI 30, small inducible cytokine subfamily A, member 22, etc. The genes encoding CD44, IFI 30, mannose receptor C type 1(MRC 1), chemokine receptor 7(CCR 7), CLK 2, syntenin and cytochrome C oxidase subunit VIII were significantly expressed in both monocytes and dendritic cells cultured with Echinacea. Conclusion : This study employed a cDNA microarray chip to elicit the immune-associated gene profile; the expression was enhanced by Echinacea in CD14+ monocytes and dendritic cells. Thus we laid the basis for the quantitative and functional analysis of genes induced by Echinacea in monocytes and monocyte-derived dendritic cells.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.695-698
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• 1998

Today SOC(system on a chip) is a trend in VLSI design society. Especially MML(merged memory Logic) process provides designers with good chances to implement SOC which is consists of DRAM, SRAM, Logic and A/D mixed mode ciruit blocks. Designers need good circuit library which is reliable and easy to tune for specific design. For this need we present semi-automated analog compiler methodology. And we aplied this design methodology to resistor-string DAC design.

• 한국생물공학회:학술대회논문집
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• 2005.04a
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• pp.465-465
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• 2005

• 한국생물공학회:학술대회논문집
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• 2005.04a
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• pp.467-467
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• 2005

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.91-94
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• 1986

In this paper, a servo motor control IC for VTR is developed using standard cell library. All the cells are designed by single metal and the 3um design rule. A desinged circuit consists of circuits which generates a switching pulse and a control reference signal in VTR. The operation of VTR chip is verified by COSMOS simulator. Finally, layout is drawn by YOSELA.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.103-106
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• 2003

An oscillatory neural network circuit has been designed and fabricated in an 0.5 ${\mu}{\textrm}{m}$ double poly CMOS technology. The proposed oscillatory neural network consists of 3 neural oscillator cells with excitatory synapses and a neural oscillator cell with inhibitory synapse. Simulations of a network of oscillators demonstrate cooperative computation. Measurements of the fabricated chip in condition of $\pm$ 2.5 V power supply is shown.

• Journal of the Korean institute of surface engineering
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• v.31 no.1
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• pp.45-53
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• 1998

Sharp tips are commonly used for applications in fields as diverse as nanolithography, lowvoltage field emitters, emitters, nanoelectroniecs, electrochemisty, cell biology, field-ion and electron microscopy. tungsten wire, mater만 used in this experiment, which test the chip of wafer has been used to the needle of probe card. Tungsten wire was sharpened by electrochemical etching methode to get a typical tip shape.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.365-368
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• 2003

In this Paper, we report a design of Serial ATA Transpor layer. The functionalities of the Serial ATA transport layer are first described on RTL via verilog. The compiled code are then fed to a synthesizer synopsys to get the actual hardware from 0.35$\mu\textrm{m}$ SAMSUNG standard cell library. The designed functionalities of this chip will be verified using test bold with FPGA equipment and ATS2 digital test equipment.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.5
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• pp.861-865
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• 1994

By using Neural Networks, a 8$\times$8 Banyan network controller is designed and implemented. In order to solve internal blocking and output blocking, Winner-Take-All method is used. The longer queue takes higher priority. First-in-first-out method is used among the non-blocking cells in the queue selected.The required time to select a cell is 2.7 $\mu$sec for 155Mbps. The implemented controller using Xilinx FPGA chip selects cells within 2.5$\mu$sec.