• Title/Summary/Keyword: Cell interconnection

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Biomass Gasification for Fuel Cell Combined-Heat-and-Power Systems (바이오매스 활용 연료전지 열병합발전시스템을 위한 연료화 공정)

  • Hong, Gi Hoon;Uhm, Sunghyun;Hwang, Sangyeon
    • Applied Chemistry for Engineering
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    • v.33 no.4
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    • pp.335-342
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    • 2022
  • In the agricultural sector where the fossil fuels are primary energy resources, the current global energy crisis together with the dissemination of smart farming has led to the new phase of energy pattern in which the electricity demand is growing faster particularly. Therefore, the fuel cell combined heat and power system, coupling the environmentally friendly fuel cell to biomass treatment and feeding, can be regarded as the most effective energy system in agriculture. In this mini-review, we discuss the R&D trend of the fuel cell combined heat and power system aimed at utilizing agricultural by-products as fuels and highlight the issues in terms of the process configuration and interconnection of individual processes.

A Clustered Reconfigurable Interconnection Network BIST Based on Signal Probabilities of Deterministic Test Sets (결정론적 테스트 세트의 신호확률에 기반을 둔 clustered reconfigurable interconnection network 내장된 자체 테스트 기법)

  • Song Dong-Sup;Kang Sungho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.12
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    • pp.79-90
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    • 2005
  • In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST to improve the embedding probabilities of random-pattern-resistant-patterns. The proposed method uses a scan-cell reordering technique based on the signal probabilities of given test cubes and specific hardware blocks that increases the embedding probabilities of care bit clustered scan chain test cubes. We have developed a simulated annealing based algorithm that maximizes the embedding probabilities of scan chain test cubes to reorder scan cells, and an iterative algorithm for synthesizing the CRIN hardware. Experimental results demonstrate that the proposed CRIN BIST technique achieves complete fault coverage with lower storage requirement and shorter testing time in comparison with the conventional methods.

A New Anti-Islanding Method for Utility Interconnection of Distributed Power Generation System (분산전원시스템의 계통연계를 위한 새로운 단독운전 방지기법)

  • Hwang In-Ho
    • The Transactions of the Korean Institute of Power Electronics
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    • v.9 no.6
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    • pp.568-576
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    • 2004
  • This paper presents a new anti-islanding method for distributed power generation system (DPGS) using renewable energy. Based on the concept of real and reactive power mismatch, three different islanding conditions are analyzed. It is shown via analysis that islanding voltage is a function of real power alone, where as its frequency is a function of both real and reactive power. Using this analysis, a new anti-islanding method is developed. The proposed protection algorithm continuously perturbs ($\pm$5%) the reactive power supplied by DPGS while simultaneously monitoring the utility voltage and frequency. If a measurable frequency deviation took place by islanding, the real power of DPGS is further reduced to 80%. This detection method is shown to be fast acting under resonant loads. Possible islanding conditions are simulated and verified with analysis. Experimental results on a 0.5kW utility-interactive fuel cell system are suggested.

Development of the Interconnection Evaluation System for Dispersed Generations in Distribution Systems (분산전원의 배전계통 연계 평가 시스템의 개발에 관한 연구)

  • Kang Min-Kwan;Park Jae-Ho;Oh Yong-Taek;Hong Sang-Eun;Rho Dae-Seok
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.7 no.1
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    • pp.12-20
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    • 2006
  • Recently, new dispersed sources (DSG) such as Photovoltaic, Wind Power, fuel cell etc. are interconnected with distribution systems as national projects for alternative energy preparing for oil crisis. This paper deals with the optimal evaluation algorithms in the case where new dispersed sources are operated in distribution systems. It is very difficult and complicated to handle the interconnection issues for proper voltage managements, because professional skills and enormous amounts of data for the evaluations are required. The typical evaluation algorithms mainly depending on individual ability and quality of data acquired, inevitably cause the different results f3r the same issue, so unfair and subjective evaluations are unavoidable. In order to overcome these problems, this paper proposes reasonable and general algorithms based on the standard model system and proper criterion, which offers the fair and objective evaluations in any case.

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A study on the architecture and logic block design of FPGA (FPGA 구조 및 로직 블록의 설계에 관한 연구)

  • 윤여환;문중석;문병모;안성근;정덕균
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.11
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    • pp.140-151
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    • 1996
  • In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

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Hardware Implementation of Discrete-Time Cellular Neural Networks Using Distributed Arithmetic (분산연산 방식을 이용한 이산시간 Cellular 신경회로망의 하드웨어 구현)

  • Park, Sung-Jun;Lim, Joon-Ho;Chae, Soo-Ik
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.1
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    • pp.153-160
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    • 1996
  • In this paper, we propose an efficient digital architecture for the discrete-time cellular neural networks (DTCNN's). DTCNN's have the locality and the translation invariance in the templates which determine the patterns of the connection between the cells. Using distributed arithmetic (DA) and the characteristics of DTCNN, we propose a simple implementation of DTCNN. The bus width in the cell-to-cell interconnection is reduced to one bit because of DA's bitwise operation. We implemented the reconfigurable architecture of DTCNN using programmable FPGA.

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VLSI Design of Data Manipulation Unit capable of bit partitioned shifts and various data type conversions (비트 분할 데이터 시프트 및 다양한 형식 변환이 가능한 데이터 처리기의 VLSI 설계)

  • 유재희
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.6C
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    • pp.594-600
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    • 2002
  • A data manipulation unit capable of bit partitioned shift and various multimedia data type conversions in addition to conventional shift, is presented. Utilizing the similarity between the data type conversion and the shift, the addition of small amount of interconnections to conventional barrel shifter enables data type conversion as well as shift operations with minimal hardware overhead. The presented data manipulation unit is composed of the shifter block for conventional shift and a pack and a unpack block. It has been designed with verilog HDL and the VLSI implementation results using compass 0.6 um standard cell are discussed.

A Novel Anti-Islanding Method for Utility Interconnection of Distributed Power Generation Systems

  • In-Ho
    • KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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    • v.4B no.4
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    • pp.217-224
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    • 2004
  • A novel anti-islanding method for the distributed power generation system (DPGS) is proposed in this paper. Three different islanding scenarios are explored and presented based on the analysis of real and reactive power mismatch. It is shown via investigation that islanding voltage is a function of real power alone, where its frequency is a function of both real and reactive power. Following this analysis, a robust anti-islanding algorithm is developed. The proposed algorithm continuously perturbs ($\pm$5%) the reactive power supplied by the DPGS while simultaneously monitoring the utility voltage and frequency. In the event of islanding, a measurable frequency deviation takes place, upon which the real power of the DPGS is further reduced to 80%. A drop in voltage positively confirms islanding and the DPGS is then safely disconnected. This method of control is shown to be robust: it is able to detect islanding under resonant loads and is also fast acting (operable in one cycle). Possible islanding conditions are simulated and verified through analysis. Experimental results on a 0.5kW fuel cell system connected to a utility grid are discussed.

Optimal Operation Scheme of MicroGrid System based on Renewable Energy Resources (신재생 에너지원 기반의 마이크로그리드 최적운영 방안)

  • Rhee, Sang-Bong;Kim, Kyu-Ho;Lee, Sang-Geun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.8
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    • pp.1467-1472
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    • 2011
  • This paper presents an optimal operation of microgrid systems and considering a tie-lines capacities that concerned each grid. The microgrid system consists of a wind turbine, a diesel generator, and a fuel cell. An one day load profile and wind resource for wind turbine generator were used for the study. For the grid interconnection, tie-line capacities were applied as constraints. The capacity constraints of tie-lines in production cost analysis are very important issues in the operation and planning of microgrid. In optimization, the Harmony Search (HS) algorithm is used for solving the problem of microgrid system operation which a various generation resources are available to meet the customer load demand with minimum operating cost. The application of HS algorithm to optimal operation of microgrid proves its effectiveness to determine optimally the generating resources without any differences of load mismatch.

Design of A Logic/Timing Extraction System for Higher-level Design Verification (상위단계 설계 검증을 위한 논리/타이밍 추출 시스템의 설계)

  • 이용재;문인호;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.2
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    • pp.76-85
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    • 1993
  • This paper describes the design of a technology-independent logic, function, and timing extraction system from SPICE-like network descriptions. Technology-independent extraction mechanism is provided in the form of technology files containing the rules for constructing logic gates and functional blocks. The designed system can be more effectively used in cell-based design by describing the cells to be extracted. Timing extraction is performed by using a linear RC gate delay model which takes interconnection delay into account. Experimental results show that estimated delay is within 10 percents for logic gate circuits when compared with SPICE. Through higher-level design descriptions obtained by extraction, design cycles can be considerably reduces.

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