• Title/Summary/Keyword: Cell array

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Impedance Analysis and Surge Characteristics of PV Array

  • Lee K.O.;So J.H.;Jung M.W;Yu G.J.;Choi J. Y.;Ah H.S.
    • Proceedings of the KIPE Conference
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    • 2003.07a
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    • pp.235-238
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    • 2003
  • Photovoltaic(PV) array, which is generally installed outside, has the possibility to be damaged by high voltage due to lightning. Because the surge characteristics of PV array have not b eon fully Identified yet, there is a very important issue whether PV array should be connected with ground or not. In this paper, a basic model of PV array is provided considering the PV cell's barrier capacitance and ground capacitance for analysis of surge characteristics.

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Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background-pattern Dependencies in Pure Memristor Array

  • Shin, SangHak;Byeon, Sang-Don;Song, Jeasang;Truong, Son Ngoc;Mo, Hyun-Sun;Kim, Deajeong;Min, Kyeong-Sik
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.685-694
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    • 2015
  • In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of $64{\times}64$, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of $128{\times}128$, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.

Liquid Crystal Lens Array with Thermally Controllable Focal Length and Electrically Convertible Lens Type

  • Heo, Kyong Chan;Kwon, Jin Hyuk;Gwag, Jin Seog
    • Journal of the Optical Society of Korea
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    • v.19 no.1
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    • pp.88-94
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    • 2015
  • This paper reports the fabrication of a lenticular liquid crystal (LC) lens array with thermally tunable focus and with the function of a convertible lens type, using the surface structure of a UV-curable polymer and a twisted-nematic (TN) LC cell. The TN LC cell makes the LC lenticular lens function as a converging or diverging lens by controlling electrically the polarization of input light. Therefore, the focal lengths for both the converging and diverging lenses, which can be switched from the TN cell, can be tuned by changing the effective refractive index of the LC by Joule heating of the transparent electrode. As a result, the focal length of the lens with the E7 LC was changed continuously from 8.7 to 31.2 mm for the converging lens type and from -9.8 to -14.2 mm for the diverging lens when the temperature was increased from 25 to $56^{\circ}C$.

Analysis of the Effects of the Irradiation and Cell-Temperature on the Dynamic Responses of PV System with MPPT (태양광의 세기와 셀 온도가 최대전력 추종을 하는 태양광 발전의 동특성에 미치는 영향 분석)

  • Loc, Nguyen Khanh;Moon, Dae-Seong;Seo, Jae-Jin;Won, Dong-Jun
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1142-1143
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    • 2008
  • As well known, the maximum power point tracking (MPPT) is an important role in photovoltaic (PV) power systems. MPPT finds and maintains the operation of PV at the maximum power point when the irradiation and cell-temperature change. In this paper, the studied system includes a PV array, a Buck-Boost DC/DC converter, a DC/AC inverter and it is connected to the three phase power system. The solar array operates as a non-linear voltage source. The P&O algorithm with power feed-back is used to control the operating point of PV array at the maximum power point. The effects of irradiation and cell-temperature on the dynamic responses are also considered.

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A High-Density 64k-Bit One-Time Programmable ROM Array with 3-Transistor Cell Standard CMOS Gate-Oxide Antifuse

  • Cha, Hyouk-Kyu;Kim, Jin-Bong;Lee, Kwy-Ro
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.2
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    • pp.106-109
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    • 2004
  • A high-density 3-transistor cell one-time programmable (OTP) ROM array using standard CMOS Gate-Oxide antifuse (AF) is proposed, fabricated, and characterized with $0.18{\mu}m$ CMOS process. The proposed non-volatile high-density OTP ROM is composed of an array of 3-T OTP cells with the 3-T consisting of an nMOS AF, a high voltage (HV) blocking transistor, and a cell access transistor, all compatible with standard CMOS technology.

Pattern Analysis of Maximum Power Point by means of Solar Cell Module Array Simulation (태양전지 모듈 어레이 시뮬레이션을 이용한 최대전력점 패턴분석)

  • Jeong, Ji-Won;Park, In-Gyu;Hwang, Kuk-Yeon;Ahn, Tae-Chon
    • Journal of the Korean Institute of Intelligent Systems
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    • v.23 no.1
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    • pp.72-79
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    • 2013
  • In the paper, a pattern analysis to decide whether the 1st local peak power point near open circuit voltage is the global peak power point or not, in case that the voltage and current at the 1st local peak power point are in a specific range, for Maximum Power Point Tracking on the photo voltaic power conversion system. When a solar cell panel array is shaded partially, multi-local peak power points can occur. That makes it hard to search the global peak power point. Through Tableau analysis using by piecewise linear solar cell model, V-I characteristic of a solar cell panel array circuit when partial shading problem happens, is simulated. The global peak power and the local peak power points is confirmed by simulations. Voltage and current values and patterns of V-I characteristic are analyzed. The generating efficiency of the solar cell panel array is improved, when the solar cell panel array circuit is operated at the power point estimated by setting up specific range.

The methods of error detection at Digital circuit using the FPGA 2-dimensional array (FPGA 2 차원 배열을 사용한 디지털 회로에서 오류 검출의 방법)

  • Kim, Soke-Hwan;Hur, Chang-Wu
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.202-206
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    • 2012
  • In this paper, we proposed on the direction of self-repairing mimicking the cell on the digital system design. Three-dimensional array of cells rather than using the original structure of FPGA, an array of blocks for efficient error detection methods were investigated. With a certain regularity, so the design method in detail by dividing the full array. The digital circuits can be detected fault location easily and quickly.

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The methods of error detection at Digital circuit using the FPGA 2-dimensional array (FPGA 2차원 배열을 사용한 디지털 회로에서 오류 검출의 방법)

  • Kim, Soke-Hwan;Hur, Chang-Wu
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.6
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    • pp.1306-1311
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    • 2012
  • In this paper, we proposed on the direction of self-repairing mimicking the cell on the digital system design. Three-dimensional array of cells rather than using the original structure of FPGA, an array of blocks for efficient error detection methods were investigated. With a certain regularity, so the design method in detail by dividing the full array. The digital circuits can be detected fault location easily and quickly.

Neuron-on-a-Chip technology: Microelectrode Array System and Neuronal Patterning (뉴런온칩 기술: 미세전극칩시스템과 신경세포 패터닝 기술)

  • Nam, Yoon-Key
    • Journal of Biomedical Engineering Research
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    • v.30 no.2
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    • pp.103-112
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    • 2009
  • Neuron-on-a-Chip technology is based on advanced neuronal culture technique, surface micropatterning, microelectrode array technology, and multi-dimensional data analysis techniques. The combination of these techniques allowed us to design and analyze live biological neural networks in vitro using real neurons. In this review article, two underlying technologies are reviewed: Microelectrode array technology and Neuronal patterning technology. There are new opportunities in the fusion of these technologies to apply them in neurobiology, neuroscience, neural prostheses, and cell-based biosensor areas.

A Study on the Resistor Array Networks for the Optimum Termination of a Modified Large TEM Cell (변형 TEM Cell의 최적 종단 처리를 위한 저항 어레이 망 설계에 관한 연구)

  • 이중근;강문수
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.7 no.2
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    • pp.157-166
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    • 1996
  • This paper presents the optimum termination method of a TEM Cell, which utilizes hybrid distributed termination resistor array networks. Current stream on the septum, and on the terminal end of a TEM Cell is analyzed by numerical analysis. By circuit analysis, the optimum resistor array network is designed based on the result of the analysis, which assures efficient power dissipation, and current stream traveling straight and uniform. Thermovision photos were taken for comparing the conventional termination network on which each resistor is arranged at regular intervals, with the suggested optimum termination network on which each resistor is arranged for current distribution. The comparison of the results of thermovision photos shows a good agreement with those obtained by numerical analysis.

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