• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.4
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• pp.31-40
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• 2022

YOLOv4 can be used for detecting parking vehicles in order to check a vehicle in out-door parking space. YOLOv4 has 9 anchor boxes in each of 13x13 grid cells for detecting a bounding box of object. Because anchor boxes are allocated based on each cell, there can be existed small observational error for detecting real objects due to the distance between neighboring cells. In this paper, we proposed YOLOv4 grid cell shift algorithm for improving the out-door parking vehicle detection accuracy. In order to get more chance for trying to object detection by reducing the errors between anchor boxes and real objects, grid cells over image can be shifted to vertical, horizontal or diagonal directions after YOLOv4 basic detection process. The experimental results show that a combined algorithm of a custom trained YOLOv4 and a cell shift algorithm has 96.6% detection accuracy compare to 94.6% of a custom trained YOLOv4 only for out door parking vehicle images.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.25-32
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• 2011

We have analyzed adjacent cell dependency of threshold voltage shift caused by the cell to cell interference, and we proposed a 3-adjacent-cell model to model the pattern dependency of the threshold voltage shift. The proposed algorithm is verified by using MATLAB simulation and measurement results. In the experimental results, we found that accuracy of the proposed simple 3-adjacient-cell model is comparable to the widely used conventional 8-adjacient-cell model. The Bit Error Rate (BER) of LSB and of MSB is improved by 28.9% and 19.8%, respectively, by applying the proposed algorithm based on 3-adjacent-cell model to 20nm-class 2-bit MLC NAND flash memories.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

• Journal of Korea Multimedia Society
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• v.17 no.12
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• pp.1418-1429
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• 2014

In this paper we suggest a new two-wheelers detection algorithm using local cell features. The first, we propose new feature vector matrix extraction algorithm using the correlation two cells based on local cell histogram and shifting from the result of histogram of oriented gradients(HOG). The second, we applied new weighting values which are calculated by the modified histogram intersection showing the similarity of two cells. This paper applied the Adaboost algorithm to make a strong classification from weak classification. In this experiment, we can get the result that the detection rate of the proposed method is higher than that of the traditional method.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.4
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• pp.3-10
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• 2005

Every cell position of a maximum-length 90/150 cellular automata(CA) generates the same pseudo-noise(PN) sequence corresponding to the characteristic polynomial of the CA with a phase shift. Unlike LFSRs, the phase shift is generally different between stages of a CA. In this paper, we propose an algorithm to compute relative phase shifts between stage of a CA. Our algorithm does not need Shank's algorithm to compute relative phase shifts and does not need any previous phase shifts to compute a phase shift. Moreover it is done in time $O(2^n)$.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.82-85
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• 1998

Because ATM was originally designed for the optical fiber environment with bit error rate(BER) of 10-11, it is difficult to maintain ATM cell extraction capability in wireless environment where BER ranges from 10-6 to 10-3. Therefore, it must be proposed the algorithm of ATM cell extraction in wereless environment. In this paper, the frame structure and synchronization algorithm satisfyling the above condition are explained, and the new ASIC implementation method of this algorithm is proposed. The known method using shift register needs so many gates that it is not suitable for ASIC implementation. But in the proposed method, a considerable reduction in gate count can be achieved by using random access memory.

• International Journal of Control, Automation, and Systems
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• v.4 no.5
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• pp.637-644
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• 2006

Biomedical image is often complex. An applied image analysis system should deal with the images which are of quite low quality and are challenging to segment. This paper presents a framework for color cell image segmentation by learning and classification online. It is a robust two-stage scheme using kernel method and watershed transform. In first stage, a two-class SVM is employed to discriminate the pixels of object from background; where the SVM is trained on the data which has been analyzed using the mean shift procedure. A real-time training strategy is also developed for SVM. In second stage, as the post-processing, local watershed transform is used to separate clustering cells. Comparison with the SSF (Scale space filter) and classical watershed-based algorithm (those are often employed for cell image segmentation) is given. Experimental results demonstrate that the new method is more accurate and robust than compared methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1267-1275
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• 2017

This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over $GF(2^{233})$, which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.158.5-158
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• 2001

Monopulse active homing radar requires velocity and angle information of target to track fast moving target. Target velocity can be estimated by measuring the frequency shift between transmitted and received frequencies. Angle information is obtained by measuring boresight error. Measurement of doppler frequency component in received signal is done through FFT analysis and interpolation algorithm for fine tuning. Boresight errors in azimuth and elevation axes are proportional to the power of each difference channel relative to sum channel. The target signal power in difference channel is estimated more precisely by measuring the power of FFT result cell of maximum ...